[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CANaxB-wkcNKWjyNGFuMn6f6H2DQSGwwQjUgg1eATdUgmM-Kg+A@mail.gmail.com>
Date: Wed, 13 Jul 2022 21:04:02 -0700
From: Andrei Vagin <avagin@...il.com>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: LKML <linux-kernel@...r.kernel.org>,
Andy Lutomirski <luto@...nel.org>,
Dave Hansen <dave.hansen@...ux.intel.com>,
Fenghua Yu <fenghua.yu@...el.com>,
Tony Luck <tony.luck@...el.com>,
Yu-cheng Yu <yu-cheng.yu@...el.com>,
Sebastian Andrzej Siewior <bigeasy@...utronix.de>,
Borislav Petkov <bp@...e.de>,
Peter Zijlstra <peterz@...radead.org>,
Kan Liang <kan.liang@...ux.intel.com>,
Chang Seok Bae <chang.seok.bae@...el.com>,
Megha Dey <megha.dey@...ux.intel.com>,
Oliver Sang <oliver.sang@...el.com>
Subject: Re: [patch V4 09/65] x86/fpu: Sanitize xstateregs_set()
On Wed, Jun 23, 2021 at 5:24 AM Thomas Gleixner <tglx@...utronix.de> wrote:
....
>
> - /*
> - * mxcsr reserved bits must be masked to zero for security reasons.
> - */
> - xsave->i387.mxcsr &= mxcsr_feature_mask;
> -
> - /*
> - * In case of failure, mark all states as init:
> - */
> - if (ret)
> - fpstate_init(&fpu->state);
> + fpu__prepare_write(fpu);
> + ret = copy_kernel_to_xstate(&fpu->state.xsave, kbuf ?: tmpbuf);
This change breaks gVisor. Now, when we set a new fpu state without
fp,sse and ymm
via ptrace, mxcsr isn't reset to the default value. The issue is
reproduced only on hosts
without xsaves. On hosts with xsaves, it works as expected.
Thanks,
Andrei
Powered by blists - more mailing lists