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Message-ID: <4812abd6-626c-67e4-7314-be282cd25a4a@intel.com>
Date: Mon, 25 Jul 2022 10:47:49 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: Andrei Vagin <avagin@...il.com>,
Thomas Gleixner <tglx@...utronix.de>
Cc: LKML <linux-kernel@...r.kernel.org>,
Andy Lutomirski <luto@...nel.org>,
Dave Hansen <dave.hansen@...ux.intel.com>,
Fenghua Yu <fenghua.yu@...el.com>,
Tony Luck <tony.luck@...el.com>,
Yu-cheng Yu <yu-cheng.yu@...el.com>,
Sebastian Andrzej Siewior <bigeasy@...utronix.de>,
Borislav Petkov <bp@...e.de>,
Peter Zijlstra <peterz@...radead.org>,
Kan Liang <kan.liang@...ux.intel.com>,
Chang Seok Bae <chang.seok.bae@...el.com>,
Megha Dey <megha.dey@...ux.intel.com>,
Oliver Sang <oliver.sang@...el.com>
Subject: Re: [patch V4 09/65] x86/fpu: Sanitize xstateregs_set()
On 7/13/22 21:04, Andrei Vagin wrote:
>> - /*
>> - * mxcsr reserved bits must be masked to zero for security reasons.
>> - */
>> - xsave->i387.mxcsr &= mxcsr_feature_mask;
>> -
>> - /*
>> - * In case of failure, mark all states as init:
>> - */
>> - if (ret)
>> - fpstate_init(&fpu->state);
>> + fpu__prepare_write(fpu);
>> + ret = copy_kernel_to_xstate(&fpu->state.xsave, kbuf ?: tmpbuf);
> This change breaks gVisor. Now, when we set a new fpu state without
> fp,sse and ymm via ptrace, mxcsr isn't reset to the default value.
> The issue is reproduced only on hosts without xsaves. On hosts with
> xsaves, it works as expected.
Is gVisor some out-of-tree kernel code or is it just an proprietary KVM
user? In other words, is this an issue with the upstream kernel itself
or does it require kernel modification?
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