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Date: Thu, 14 Jul 2022 18:34:41 +0800
From: CK Hu <ck.hu@...iatek.com>
To: Rex-BC Chen <rex-bc.chen@...iatek.com>,
"chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>,
"p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
"daniel@...ll.ch" <daniel@...ll.ch>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>,
"mripard@...nel.org" <mripard@...nel.org>,
"tzimmermann@...e.de" <tzimmermann@...e.de>,
"matthias.bgg@...il.com" <matthias.bgg@...il.com>,
"deller@....de" <deller@....de>,
"airlied@...ux.ie" <airlied@...ux.ie>
CC: "msp@...libre.com" <msp@...libre.com>,
"granquet@...libre.com" <granquet@...libre.com>,
Jitao Shi (石记涛)
<jitao.shi@...iatek.com>,
"wenst@...omium.org" <wenst@...omium.org>,
"angelogioacchino.delregno@...labora.com"
<angelogioacchino.delregno@...labora.com>,
LiangXu Xu (徐亮)
<LiangXu.Xu@...iatek.com>,
"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
"linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-fbdev@...r.kernel.org" <linux-fbdev@...r.kernel.org>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [PATCH v14 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort
driver
Hi, Bo-Chen:
On Thu, 2022-07-14 at 17:09 +0800, Rex-BC Chen wrote:
> On Thu, 2022-07-14 at 14:51 +0800, CK Hu wrote:
> > Hi, Bo-Chen:
> >
> > On Tue, 2022-07-12 at 19:12 +0800, Bo-Chen Chen wrote:
> > > From: Markus Schneider-Pargmann <msp@...libre.com>
> > >
> > > This patch adds a embedded displayport driver for the MediaTek
> > > mt8195
> > > SoC.
> > >
> > > It supports the MT8195, the embedded DisplayPort units. It offers
> > > DisplayPort 1.4 with up to 4 lanes.
> > >
> > > The driver creates a child device for the phy. The child device
> > > will
> > > never exist without the parent being active. As they are sharing
> > > a
> > > register range, the parent passes a regmap pointer to the child
> > > so
> > > that
> > > both can work with the same register range. The phy driver sets
> > > device
> > > data that is read by the parent to get the phy device that can be
> > > used
> > > to control the phy properties.
> > >
> > > This driver is based on an initial version by
> > > Jitao shi <jitao.shi@...iatek.com>
> > >
> > > Signed-off-by: Markus Schneider-Pargmann <msp@...libre.com>
> > > Signed-off-by: Guillaume Ranquet <granquet@...libre.com>
> > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@...iatek.com>
> > > ---
> >
> > [snip]
> >
> > > +static int mtk_dp_train_tps_2_3(struct mtk_dp *mtk_dp, u8
> > > target_linkrate,
> > > + u8 target_lane_count, int
> > > *iteration_count,
> > > + u8 *lane_adjust, int *status_control,
> > > + u8 *prev_lane_adjust)
> > > +{
> > > + u8 val;
> > > + u8 link_status[DP_LINK_STATUS_SIZE] = {};
> > > +
> > > + if (*status_control == 1) {
> > > + if (mtk_dp->train_info.tps4) {
> > > + mtk_dp_train_set_pattern(mtk_dp, 4);
> > > + val = DP_TRAINING_PATTERN_4;
> > > + } else if (mtk_dp->train_info.tps3) {
> > > + mtk_dp_train_set_pattern(mtk_dp, 3);
> > > + val = DP_LINK_SCRAMBLING_DISABLE |
> > > + DP_TRAINING_PATTERN_3;
> > > + } else {
> > > + mtk_dp_train_set_pattern(mtk_dp, 2);
> > > + val = DP_LINK_SCRAMBLING_DISABLE |
> > > + DP_TRAINING_PATTERN_2;
> > > + }
> > > + drm_dp_dpcd_writeb(&mtk_dp->aux,
> > > + DP_TRAINING_PATTERN_SET, val);
> > > + drm_dp_dpcd_read(&mtk_dp->aux,
> > > + DP_ADJUST_REQUEST_LANE0_1,
> > > lane_adjust,
> > > + sizeof(*lane_adjust) * 2);
> > > +
> > > + mtk_dp_train_update_swing_pre(mtk_dp,
> > > + target_lane_count,
> > > lane_adjust);
> > > + *status_control = 2;
> > > + (*iteration_count)++;
> > > + }
> > > +
> > > + drm_dp_link_train_channel_eq_delay(&mtk_dp->aux, mtk_dp-
> > > > rx_cap);
> > >
> > > +
> > > + drm_dp_dpcd_read_link_status(&mtk_dp->aux, link_status);
> > > +
> > > + if (!drm_dp_clock_recovery_ok(link_status, target_lane_count))
> >
> > I think this checking is redundant. I think we could just keep
> > drm_dp_channel_eq_ok() and drop drm_dp_clock_recovery_ok() here
> > because
> > if drm_dp_clock_recovery_ok() fail, it imply that
> > drm_dp_channel_eq_ok() would fail. So just check
> > drm_dp_channel_eq_ok()
> > is enough.
> >
> > Regards,
> > CK
> >
> > > {
> > > + mtk_dp->train_info.cr_done = false;
> > > + mtk_dp->train_info.eq_done = false;
> > > + dev_dbg(mtk_dp->dev, "Link train EQ fail\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + if (drm_dp_channel_eq_ok(link_status, target_lane_count)) {
> > > + mtk_dp->train_info.eq_done = true;
> > > + dev_dbg(mtk_dp->dev, "Link train EQ pass\n");
> > > + return 0;
> > > + }
> > > +
>
> Hello CK,
>
> do you mean like this?
> if (drm_dp_channel_eq_ok(link_status, target_lane_count)) {
> mtk_dp-
> > train_info.eq_done = true;
>
> dev_dbg(mtk_dp->dev, "Link train EQ pass\n");
> return 0;
> } else {
> mtk_dp->train_info.cr_done = false;
> mtk_dp->train_info.eq_done = false;
> dev_dbg(mtk_dp->dev, "Link train EQ fail\n");
> return -EINVAL;
> }
No, I mean just remove drm_dp_clock_recovery_ok() checking. When
drm_dp_channel_eq_ok() fail, it should keep retry. If clock recovery
has some problem, drm_dp_channel_eq_ok() would be finally out of retry
count.
Regards,
CK
>
> BRs,
> Bo-Chen
>
> > > + if (*prev_lane_adjust == link_status[4])
> > > + (*iteration_count)++;
> > > + else
> > > + *prev_lane_adjust = link_status[4];
> > > +
> > > + return -EAGAIN;
> > > +}
> > > +
> >
> >
>
>
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