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Message-ID: <YtGNnT2cP5HIayp3@sirena.org.uk>
Date: Fri, 15 Jul 2022 16:54:05 +0100
From: Mark Brown <broonie@...nel.org>
To: "Mahapatra, Amit Kumar" <amit.kumar-mahapatra@....com>
Cc: Amit Kumar Mahapatra <amit.kumar-mahapatra@...inx.com>,
"p.yadav@...com" <p.yadav@...com>,
"miquel.raynal@...tlin.com" <miquel.raynal@...tlin.com>,
"richard@....at" <richard@....at>,
"vigneshr@...com" <vigneshr@...com>,
"git@...inx.com" <git@...inx.com>,
"michal.simek@...inx.com" <michal.simek@...inx.com>,
"linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"michael@...le.cc" <michael@...le.cc>,
"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
"git (AMD-Xilinx)" <git@....com>
Subject: Re: [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI
device
On Fri, Jul 15, 2022 at 03:35:49PM +0000, Mahapatra, Amit Kumar wrote:
> > That doesn't address the issue, the issue is checking that the driver can
> > support multiple chip selects.
> To address this issue, in spi core we will check the number of items
> in the "reg" property of the flash node(which is nothing but the
> number of chip selects) against the "num-cs" property of the spi
> controller(which is total number of chip selects supported by the
> controller). If the number of items mentioned in the "reg" property
> is greater than "num-cs" value then we error out.
> For eg.,
> rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
> SPI_CS_CNT_MAX);
> if(rc > ctlr->num_chipselect) {
> dev_err(&ctlr->dev, "%pOF has invalid 'reg' property (%d)\n",
> nc, rc);
> return -EINVAL;
> }
This would check that the controller has at least the number of chip
selects specified but it would not check that the controller is actually
capable of using more than one chip select at once. We should be
validating both that the chip selects are available and that the
controller can do something useful with them (and probably have an
implementation in the core for doing so via GPIO).
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