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Message-ID: <CABb+yY1i0qUOptrBJWj05t4-MCtmsC+AhCR8udoxLAe+pygZiQ@mail.gmail.com> Date: Sun, 17 Jul 2022 09:33:07 -0500 From: Jassi Brar <jassisinghbrar@...il.com> To: Wojciech Bartczak <wbartczak@...vell.com> Cc: Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, wbartczak@...il.com, Piyush Malgujar <pmalgujar@...vell.com>, Sunil Goutham <sgoutham@...vell.com>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Devicetree List <devicetree@...r.kernel.org> Subject: Re: [PATCH 1/2] dt-bindings: mailbox : marvell,mbox: Add bindings On Thu, Jul 14, 2022 at 7:13 AM Wojciech Bartczak <wbartczak@...vell.com> wrote: ... > +description: > + The Marvell's Message Handling Unit is a mailbox controller > + with a single channel used to communicate with System Control Processor. > + Driver supports series of cn9x and cn10x SoC. > + Sole purpose of the link is to exchange SCMI related data with SCP. > + The link has hardwired configuration, it uses simple notification scheme > + over shared memory block to push data back and forth. > + Interrupts used by mailbox may be configured in two ways, > + as SPI interrupts, then driver uses platform device forntend. > + Other way is to use PCI bus frontend with LPI interrupts. > + Also have a provision of SPI vs LPI mode hint via DT. ... > + > +examples: > + - | > + soc@0 { > + reg = <0 0>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + sram@36,0 { > + compatible = "cpc-shmem"; > + reg = <0x86d0 0xdd400 0 0x200>; > + #address-cells = <2>; > + #size-cells = <1>; > + ranges = <0 0x0 0x86d0 0xdd400 0x200>; > + > + scp_to_cpu0: scp-shmame@0 { > Just curious, what does 'scp-shmame' stand for? thanks.
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