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Date: Mon, 18 Jul 2022 10:58:16 +0300
From: Georgi Djakov <djakov@...nel.org>
To: Luca Weiss <luca.weiss@...rphone.com>,
linux-arm-msm@...r.kernel.org
Cc: ~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 5/5] arm64: dts: qcom: sm6350: Add interconnect support
On 25.05.22 17:44, Luca Weiss wrote:
> Add all the different NoC providers that are found in SM6350 and
> populate different nodes that use the interconnect properties.
>
> Signed-off-by: Luca Weiss <luca.weiss@...rphone.com>
> ---
> Changes since v2:
> * none
>
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 109 +++++++++++++++++++++++++++
> 1 file changed, 109 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index fb1a0f662575..119073f19285 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1,11 +1,13 @@
> // SPDX-License-Identifier: BSD-3-Clause
> /*
> * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@...ainline.org>
> + * Copyright (c) 2022, Luca Weiss <luca.weiss@...rphone.com>
> */
>
> #include <dt-bindings/clock/qcom,gcc-sm6350.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interconnect/qcom,sm6350.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/mailbox/qcom-ipcc.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> @@ -539,6 +541,10 @@ i2c0: i2c@...000 {
> interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
>
> @@ -552,6 +558,10 @@ i2c2: i2c@...000 {
> interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
> };
> @@ -578,6 +588,10 @@ i2c6: i2c@...000 {
> interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
>
> @@ -591,6 +605,10 @@ i2c7: i2c@...000 {
> interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
>
> @@ -604,6 +622,10 @@ i2c8: i2c@...000 {
> interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
>
> @@ -615,6 +637,9 @@ uart9: serial@...000 {
> pinctrl-names = "default";
> pinctrl-0 = <&qup_uart9_default>;
> interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
> + interconnect-names = "qup-core", "qup-config";
> status = "disabled";
> };
>
> @@ -628,11 +653,62 @@ i2c10: i2c@...000 {
> interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
>
> };
>
> + config_noc: interconnect@...0000 {
> + compatible = "qcom,sm6350-config-noc";
> + reg = <0 0x01500000 0 0x28000>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + system_noc: interconnect@...0000 {
> + compatible = "qcom,sm6350-system-noc";
> + reg = <0 0x01620000 0 0x17080>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> +
> + clk_virt: interconnect-clk-virt {
> + compatible = "qcom,sm6350-clk-virt";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> + };
> +
> + aggre1_noc: interconnect@...0000 {
> + compatible = "qcom,sm6350-aggre1-noc";
> + reg = <0 0x016e0000 0 0x15080>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + aggre2_noc: interconnect@...0000 {
> + compatible = "qcom,sm6350-aggre2-noc";
> + reg = <0 0x01700000 0 0x1f880>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> +
> + compute_noc: interconnect-compute-noc {
> + compatible = "qcom,sm6350-compute-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> + };
> +
> + mmss_noc: interconnect@...0000 {
> + compatible = "qcom,sm6350-mmss-noc";
> + reg = <0 0x01740000 0 0x1c100>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> ufs_mem_hc: ufs@...4000 {
> compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
> "jedec,ufs-2.0";
> @@ -933,6 +1009,10 @@ sdhc_2: sdhci@...4000 {
> <&gcc GCC_SDCC2_APPS_CLK>,
> <&rpmhcc RPMH_CXO_CLK>;
> clock-names = "iface", "core", "xo";
> + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
> + interconnect-names = "sdhc-ddr", "cpu-sdhc";
> +
> qcom,dll-config = <0x0007642c>;
> qcom,ddr-config = <0x80040868>;
> power-domains = <&rpmhpd 0>;
> @@ -947,11 +1027,15 @@ sdhc2_opp_table: sdhc2-opp-table {
> opp-100000000 {
> opp-hz = /bits/ 64 <100000000>;
> required-opps = <&rpmhpd_opp_svs_l1>;
> + opp-peak-kBps = <790000 131000>;
> + opp-avg-kBps = <50000 50000>;
> };
>
> opp-202000000 {
> opp-hz = /bits/ 64 <202000000>;
> required-opps = <&rpmhpd_opp_nom>;
> + opp-peak-kBps = <3190000 294000>;
> + opp-avg-kBps = <261438 300000>;
Just wondering where do these values come from? Are they from the downstream DT?
The rest looks good to me.
Thanks,
Georgi
> };
> };
> };
> @@ -1017,12 +1101,33 @@ dp_phy: dp-phy@...a200 {
> };
> };
>
> + dc_noc: interconnect@...0000 {
> + compatible = "qcom,sm6350-dc-noc";
> + reg = <0 0x09160000 0 0x3200>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> system-cache-controller@...0000 {
> compatible = "qcom,sm6350-llcc";
> reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
> reg-names = "llcc_base", "llcc_broadcast_base";
> };
>
> + gem_noc: interconnect@...0000 {
> + compatible = "qcom,sm6350-gem-noc";
> + reg = <0 0x09680000 0 0x3e200>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + npu_noc: interconnect@...0000 {
> + compatible = "qcom,sm6350-npu-noc";
> + reg = <0 0x09990000 0 0x1600>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> usb_1: usb@...8800 {
> compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
> reg = <0 0x0a6f8800 0 0x400>;
> @@ -1051,6 +1156,10 @@ usb_1: usb@...8800 {
>
> resets = <&gcc GCC_USB30_PRIM_BCR>;
>
> + interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
> + interconnect-names = "usb-ddr", "apps-usb";
> +
> usb_1_dwc3: usb@...0000 {
> compatible = "snps,dwc3";
> reg = <0 0x0a600000 0 0xcd00>;
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