lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Mon, 18 Jul 2022 16:35:49 +0100
From:   Ken Moffat <zarniwhoop@...world.com>
To:     Alexandre Chartre <alexandre.chartre@...cle.com>
Cc:     linux-kernel@...r.kernel.org
Subject: Re: Retbleed, Zen2 and STIBP

On Mon, Jul 18, 2022 at 04:58:49PM +0200, Alexandre Chartre wrote:
> On Mon, Jul 18, 2022 at 09:19:01AM +0100, Ken Moffat wrote:
> > Probably like most people, I find the detail of the available
> > retbleed mitigations obscure.  In particular, for zen2 the options
> > *might* include ibpb or unret.
> > 
> > But I have failed to find what 'unret' actually means.  Any
> > pointers, please ?
> > 
> > While ibpb might be available (and slow), on my Renoir with
> > microcode level (0860106h) there were no newer microcode versions
> > available when I last looked (a few weeks ago) but note 7 at the
> > bottom of
> > https://www.amd.com/system/files/documents/technical-guidance-for-mitigating-branch-type-confusion_v
> > 7_20220712.pdf
> > implies that the relevant bit is only set on Renoir in 0860109h and
> > later.
> > 
> > Some of the text in that pdf implies that at least one of the
> > options could be set if not already set from the microcode, but the
> > amount of detail leaves me totally lost.
> > 
> > Assuming, for the moment, that I might want to try this full
> > mitigation, is there any way to set this in the absence of newer
> > microcode ?
> > 
> > Or should I just accept that the best I can get is 'unret', whatever
> > that means ?
> > 
> > ĸen
> 
> 'unret' = AMD JMP2RET i.e. replace all 'ret' instructions with
> 'jmp __x86_return_thunk', and safe training the thunk code upon
> kernel/hypervisor entry. This is a purely software mitigation,
> it doesn't require any microcode.
> 
> AMD JMP2RET is described in this document:
> https://www.amd.com/system/files/documents/technical-guidance-for-mitigating-branch-type-confusion_v7_20220712.pdf
> 
> alex.

Thanks!

ĸen
-- 
 It is very easy to get ridiculously confused about the tenses of
 time travel, but most things can be resolved by a sufficiently
 large ego.        -- The Last Continent

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ