| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Tue, 19 Jul 2022 15:38:44 +0300
From: Vladimir Oltean <olteanv@...il.com>
To: Christian Marangi <ansuelsmth@...il.com>
Cc: Andrew Lunn <andrew@...n.ch>,
Vivien Didelot <vivien.didelot@...il.com>,
Florian Fainelli <f.fainelli@...il.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jens Axboe <axboe@...nel.dk>, linux-kernel@...r.kernel.org,
netdev@...r.kernel.org
Subject: Re: [net-next PATCH v2 03/15] net: dsa: qca8k: move qca8k
read/write/rmw and reg table to common code
On Tue, Jul 19, 2022 at 02:57:13AM +0200, Christian Marangi wrote:
> The same reg table and read/write/rmw function are used by drivers
> based on qca8k family switch.
> Move them to common code to make it accessible also by other drivers.
>
> Signed-off-by: Christian Marangi <ansuelsmth@...il.com>
> ---
Note for this and future patches: I can't actually double-check what is
indeed common with ipq4019 and what isn't, I'll just review the
correctness of the movement.
In this case
Reviewed-by: Vladimir Oltean <olteanv@...il.com>
with one comment below
> drivers/net/dsa/qca/qca8k-8xxx.c | 42 ------------------------------
> drivers/net/dsa/qca/qca8k-common.c | 39 +++++++++++++++++++++++++++
> drivers/net/dsa/qca/qca8k.h | 6 +++++
> 3 files changed, 45 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c
> index 3f6c1427734d..46c371f5decc 100644
> --- a/drivers/net/dsa/qca/qca8k-8xxx.c
> +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
> @@ -133,24 +133,6 @@ qca8k_set_page(struct qca8k_priv *priv, u16 page)
> return 0;
> }
>
> -static int
> -qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
> -{
> - return regmap_read(priv->regmap, reg, val);
> -}
> -
> -static int
> -qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
> -{
> - return regmap_write(priv->regmap, reg, val);
> -}
> -
> -static int
> -qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
> -{
> - return regmap_update_bits(priv->regmap, reg, mask, write_val);
> -}
> -
> static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)
> {
> struct qca8k_mgmt_eth_data *mgmt_eth_data;
> @@ -483,30 +465,6 @@ qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_
> return ret;
> }
>
> -static const struct regmap_range qca8k_readable_ranges[] = {
> - regmap_reg_range(0x0000, 0x00e4), /* Global control */
> - regmap_reg_range(0x0100, 0x0168), /* EEE control */
> - regmap_reg_range(0x0200, 0x0270), /* Parser control */
> - regmap_reg_range(0x0400, 0x0454), /* ACL */
> - regmap_reg_range(0x0600, 0x0718), /* Lookup */
> - regmap_reg_range(0x0800, 0x0b70), /* QM */
> - regmap_reg_range(0x0c00, 0x0c80), /* PKT */
> - regmap_reg_range(0x0e00, 0x0e98), /* L3 */
> - regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
> - regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
> - regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
> - regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
> - regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
> - regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
> - regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
> -
> -};
> -
> -static const struct regmap_access_table qca8k_readable_table = {
> - .yes_ranges = qca8k_readable_ranges,
> - .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
> -};
> -
> static struct regmap_config qca8k_regmap_config = {
> .reg_bits = 16,
> .val_bits = 32,
> diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k-common.c
> index 7a63e96c8c08..1c2169e98f10 100644
> --- a/drivers/net/dsa/qca/qca8k-common.c
> +++ b/drivers/net/dsa/qca/qca8k-common.c
> @@ -61,3 +61,42 @@ const struct qca8k_mib_desc ar8327_mib[] = {
> MIB_DESC(1, 0xa8, "RXUnicast"),
> MIB_DESC(1, 0xac, "TXUnicast"),
> };
> +
> +int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
> +{
> + return regmap_read(priv->regmap, reg, val);
> +}
> +
> +int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
> +{
> + return regmap_write(priv->regmap, reg, val);
> +}
> +
> +int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
> +{
> + return regmap_update_bits(priv->regmap, reg, mask, write_val);
> +}
> +
> +static const struct regmap_range qca8k_readable_ranges[] = {
> + regmap_reg_range(0x0000, 0x00e4), /* Global control */
> + regmap_reg_range(0x0100, 0x0168), /* EEE control */
> + regmap_reg_range(0x0200, 0x0270), /* Parser control */
> + regmap_reg_range(0x0400, 0x0454), /* ACL */
> + regmap_reg_range(0x0600, 0x0718), /* Lookup */
> + regmap_reg_range(0x0800, 0x0b70), /* QM */
> + regmap_reg_range(0x0c00, 0x0c80), /* PKT */
> + regmap_reg_range(0x0e00, 0x0e98), /* L3 */
> + regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
> + regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
> + regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
> + regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
> + regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
> + regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
> + regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
> +
Please delete the extra newline.
> +};
> +
> +const struct regmap_access_table qca8k_readable_table = {
> + .yes_ranges = qca8k_readable_ranges,
> + .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
> +};
> diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h
> index 0c9b60555670..20cceac494eb 100644
> --- a/drivers/net/dsa/qca/qca8k.h
> +++ b/drivers/net/dsa/qca/qca8k.h
> @@ -419,5 +419,11 @@ struct qca8k_fdb {
>
> /* Common setup function */
> extern const struct qca8k_mib_desc ar8327_mib[];
> +extern const struct regmap_access_table qca8k_readable_table;
> +
> +/* Common read/write/rmw function */
> +int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val);
> +int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val);
> +int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val);
>
> #endif /* __QCA8K_H */
> --
> 2.36.1
>
Powered by blists - more mailing lists