linux-kernel - RE: [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI device

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Date:   Tue, 19 Jul 2022 13:21:41 +0000
From:   "Mahapatra, Amit Kumar" <amit.kumar-mahapatra@....com>
To:     Mark Brown <broonie@...nel.org>
CC:     Amit Kumar Mahapatra <amit.kumar-mahapatra@...inx.com>,
        "p.yadav@...com" <p.yadav@...com>,
        "miquel.raynal@...tlin.com" <miquel.raynal@...tlin.com>,
        "richard@....at" <richard@....at>,
        "vigneshr@...com" <vigneshr@...com>,
        "git@...inx.com" <git@...inx.com>,
        "michal.simek@...inx.com" <michal.simek@...inx.com>,
        "linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "michael@...le.cc" <michael@...le.cc>,
        "linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
        "git (AMD-Xilinx)" <git@....com>
Subject: RE: [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI
 device

Hello Mark,

> -----Original Message-----
> From: Mark Brown <broonie@...nel.org>
> Sent: Friday, July 15, 2022 9:24 PM
> To: Mahapatra, Amit Kumar <amit.kumar-mahapatra@....com>
> Cc: Amit Kumar Mahapatra <amit.kumar-mahapatra@...inx.com>;
> p.yadav@...com; miquel.raynal@...tlin.com; richard@....at;
> vigneshr@...com; git@...inx.com; michal.simek@...inx.com; linux-
> spi@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-
> kernel@...r.kernel.org; michael@...le.cc; linux-mtd@...ts.infradead.org;
> git (AMD-Xilinx) <git@....com>
> Subject: Re: [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI
> device
> 
> On Fri, Jul 15, 2022 at 03:35:49PM +0000, Mahapatra, Amit Kumar wrote:
> 
> > > That doesn't address the issue, the issue is checking that the
> > > driver can support multiple chip selects.
> 
> > To address this issue, in spi core we will check the number of items
> > in the "reg" property of the flash node(which is nothing but the
> > number of chip selects) against the "num-cs" property of the spi
> > controller(which is total number of chip selects supported by the
> > controller). If the number of items mentioned in the "reg" property is
> > greater than "num-cs" value then we error out.
> 
> > For eg.,
> 
> > rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
> > 						SPI_CS_CNT_MAX);
> > if(rc > ctlr->num_chipselect) {
> > 	dev_err(&ctlr->dev, "%pOF has invalid 'reg' property (%d)\n",
> > 							nc, rc);
> > 	return -EINVAL;
> > }
> 
> This would check that the controller has at least the number of chip selects
> specified but it would not check that the controller is actually capable of
> using more than one chip select at once. We should be validating both that

I agree, so for checking the controller multiple chip select capability(using 
more than one chip select at once) we can define a new spi controller DT 
property like "multi-cs-cap"(please suggest a better name). 
The controller that can support multiple chip selects should have this property 
in the spi controller DT node. The spi core will check ctlr->multi-cs-cap to 
operate multiple chip select in parallel.

> the chip selects are available and that the controller can do something useful
> with them (and probably have an implementation in the core for doing so via
> GPIO).

Here are you referring to the usecase in which a controller implementing multi CS
support using GPIO?  


Regards,
Amit