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Message-ID: <YtbvlYZoRDz6i+pS@sirena.org.uk>
Date: Tue, 19 Jul 2022 18:53:25 +0100
From: Mark Brown <broonie@...nel.org>
To: "Mahapatra, Amit Kumar" <amit.kumar-mahapatra@....com>
Cc: Amit Kumar Mahapatra <amit.kumar-mahapatra@...inx.com>,
"p.yadav@...com" <p.yadav@...com>,
"miquel.raynal@...tlin.com" <miquel.raynal@...tlin.com>,
"richard@....at" <richard@....at>,
"vigneshr@...com" <vigneshr@...com>,
"git@...inx.com" <git@...inx.com>,
"michal.simek@...inx.com" <michal.simek@...inx.com>,
"linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"michael@...le.cc" <michael@...le.cc>,
"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
"git (AMD-Xilinx)" <git@....com>
Subject: Re: [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI
device
On Tue, Jul 19, 2022 at 01:21:41PM +0000, Mahapatra, Amit Kumar wrote:
> I agree, so for checking the controller multiple chip select capability(using
> more than one chip select at once) we can define a new spi controller DT
> property like "multi-cs-cap"(please suggest a better name).
> The controller that can support multiple chip selects should have this property
> in the spi controller DT node. The spi core will check ctlr->multi-cs-cap to
> operate multiple chip select in parallel.
I'm not sure this needs to be a DT property, it's more just something we
infer from the compatible. The name seems fine, as does the flag in the
controller data.
> > the chip selects are available and that the controller can do something useful
> > with them (and probably have an implementation in the core for doing so via
> > GPIO).
> Here are you referring to the usecase in which a controller implementing multi CS
> support using GPIO?
Yes, we probably ought to.
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