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Message-Id: <20220719054729.2224766-3-apatel@ventanamicro.com>
Date: Tue, 19 Jul 2022 11:17:29 +0530
From: Anup Patel <apatel@...tanamicro.com>
To: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>
Cc: Atish Patra <atishp@...shpatra.org>,
Samuel Holland <samuel@...lland.org>,
Anup Patel <anup@...infault.org>, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Anup Patel <apatel@...tanamicro.com>
Subject: [PATCH 2/2] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT property
We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only when
riscv,timer-always-on DT property is not present for the corresponding
CPU.
This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device
based on RISC-V platform capabilities rather than having it set for
all RISC-V platforms.
Signed-off-by: Anup Patel <apatel@...tanamicro.com>
---
drivers/clocksource/timer-riscv.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 593d5a957b69..3015324f2b59 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -34,7 +34,7 @@ static int riscv_clock_next_event(unsigned long delta,
static unsigned int riscv_clock_event_irq;
static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
.name = "riscv_timer_clockevent",
- .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP,
+ .features = CLOCK_EVT_FEAT_ONESHOT,
.rating = 100,
.set_next_event = riscv_clock_next_event,
};
@@ -65,9 +65,13 @@ static struct clocksource riscv_clocksource = {
static int riscv_timer_starting_cpu(unsigned int cpu)
{
struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
+ struct device_node *np = of_get_cpu_node(cpu, NULL);
ce->cpumask = cpumask_of(cpu);
ce->irq = riscv_clock_event_irq;
+ if (!of_property_read_bool(np, "riscv,timer-always-on"))
+ ce->features |= CLOCK_EVT_FEAT_C3STOP;
+ of_node_put(np);
clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
enable_percpu_irq(riscv_clock_event_irq,
--
2.34.1
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