linux-kernel - Re: [PATCH 2/2] clocksource: timer-riscv: Set CLOCK_EVT_FEAT

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Date:   Tue, 19 Jul 2022 01:42:47 -0500
From:   Samuel Holland <samuel@...lland.org>
To:     Anup Patel <apatel@...tanamicro.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Atish Patra <atishp@...shpatra.org>,
        Anup Patel <anup@...infault.org>, devicetree@...r.kernel.org,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP
 based on DT property

Hi Anup,

On 7/19/22 12:47 AM, Anup Patel wrote:
> We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only when
> riscv,timer-always-on DT property is not present for the corresponding
> CPU.

The timer maintaining its context (and continuing to count) during non-retentive
CPU suspend is not sufficient to drop CLOCK_EVT_FEAT_C3STOP.

Another requirement is that the timer interrupt is generated and routed outside
the CPU's power/reset domain, to whatever hardware is responsible for turning
the CPU back on. It does not matter if the timer interrupt fires, if that
interrupt cannot wake up the CPU.

So something closer to "riscv,timer-can-wake-cpu" would be a more accurate
property name for how you are using it.

And even then, that ability is a property of the SBI implementation, not just
the hardware. In the motivating example for the flag (Allwinner D1), the CLINT
cannot wake the CPU from reset, but the SoC contains other MMIO timers that can.
So the capability of the SBI timer extension depends on which timer hardware the
SBI implementation chooses to use. So I am not sure that the property belongs in
the CPU node.

Maybe it makes sense to report this capability via a function in the SBI timer
extension?

Regards,
Samuel

> This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device
> based on RISC-V platform capabilities rather than having it set for
> all RISC-V platforms.
> 
> Signed-off-by: Anup Patel <apatel@...tanamicro.com>
> ---
>  drivers/clocksource/timer-riscv.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index 593d5a957b69..3015324f2b59 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -34,7 +34,7 @@ static int riscv_clock_next_event(unsigned long delta,
>  static unsigned int riscv_clock_event_irq;
>  static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
>  	.name			= "riscv_timer_clockevent",
> -	.features		= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP,
> +	.features		= CLOCK_EVT_FEAT_ONESHOT,
>  	.rating			= 100,
>  	.set_next_event		= riscv_clock_next_event,
>  };
> @@ -65,9 +65,13 @@ static struct clocksource riscv_clocksource = {
>  static int riscv_timer_starting_cpu(unsigned int cpu)
>  {
>  	struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
> +	struct device_node *np = of_get_cpu_node(cpu, NULL);
>  
>  	ce->cpumask = cpumask_of(cpu);
>  	ce->irq = riscv_clock_event_irq;
> +	if (!of_property_read_bool(np, "riscv,timer-always-on"))
> +		ce->features |= CLOCK_EVT_FEAT_C3STOP;
> +	of_node_put(np);
>  	clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
>  
>  	enable_percpu_irq(riscv_clock_event_irq,
>