linux-kernel - Re: [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 21 Jul 2022 12:06:56 +0100
From:   "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To:     Geert Uytterhoeven <geert@...ux-m68k.org>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
        Magnus Damm <magnus.damm@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Biju Das <biju.das.jz@...renesas.com>
Subject: Re: [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY
 interrupt support for ETH{0/1}

Hi Geert,

Thank you for the review.

On Thu, Jul 21, 2022 at 11:47 AM Geert Uytterhoeven
<geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@...renesas.com> wrote:
> > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
> > and ETH1 respectively.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 {
> >                 compatible = "ethernet-phy-id0022.1640",
> >                              "ethernet-phy-ieee802.3-c22";
> >                 reg = <7>;
> > +               interrupt-parent = <&irqc>;
> > +               interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
>
> 2?
>
IRQ2 = SPI 3, the driver expects the SPI number and is used as index
[0] to map the interrupt in the GIC.

[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?h=next-20220720#n291

> "The first cell should contain external interrupt number (IRQ0-7)"
>
Probably I need to reword this to "The first cell should contain the
SPI number for IRQ0-7/NMI interrupt lines" ?


> >                 rxc-skew-psec = <2400>;
> >                 txc-skew-psec = <2400>;
> >                 rxdv-skew-psec = <0>;
> > @@ -120,6 +122,8 @@ phy1: ethernet-phy@7 {
> >                 compatible = "ethernet-phy-id0022.1640",
> >                              "ethernet-phy-ieee802.3-c22";
> >                 reg = <7>;
> > +               interrupt-parent = <&irqc>;
> > +               interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
>
> 3?
>
IRQ3 = SPI 4

Cheers,
Prabhakar
> >                 rxc-skew-psec = <2400>;
> >                 txc-skew-psec = <2400>;
> >                 rxdv-skew-psec = <0>;
> > @@ -171,7 +175,8 @@ eth0_pins: eth0 {
> >                          <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
> >                          <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
> >                          <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
> > -                        <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
> > +                        <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
> > +                        <RZG2L_PORT_PINMUX(1, 0, 1)>;  /* IRQ2 */
> >         };
> >
> >         eth1_pins: eth1 {
> > @@ -189,7 +194,8 @@ eth1_pins: eth1 {
> >                          <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
> >                          <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
> >                          <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
> > -                        <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
> > +                        <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
> > +                        <RZG2L_PORT_PINMUX(1, 1, 1)>;  /* IRQ3 */
> >         };
> >
> >         gpio-sd0-pwr-en-hog {
> > --
> > 2.25.1
> >
>
>
> --
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds