linux-kernel - Re: [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAMuHMdWcj2xv8FrCiTLCVQfWzejONCAv_o-VzAkicLAFNd5gPg@mail.gmail.com>
Date:   Thu, 21 Jul 2022 13:43:19 +0200
From:   Geert Uytterhoeven <geert@...ux-m68k.org>
To:     "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
        Magnus Damm <magnus.damm@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Biju Das <biju.das.jz@...renesas.com>
Subject: Re: [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY
 interrupt support for ETH{0/1}

Hi Prabhakar,

On Thu, Jul 21, 2022 at 1:07 PM Lad, Prabhakar
<prabhakar.csengg@...il.com> wrote:
> On Thu, Jul 21, 2022 at 11:47 AM Geert Uytterhoeven
> <geert@...ux-m68k.org> wrote:
> > On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@...renesas.com> wrote:
> > > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
> > > and ETH1 respectively.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 {
> > >                 compatible = "ethernet-phy-id0022.1640",
> > >                              "ethernet-phy-ieee802.3-c22";
> > >                 reg = <7>;
> > > +               interrupt-parent = <&irqc>;
> > > +               interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> >
> > 2?
> >
> IRQ2 = SPI 3, the driver expects the SPI number and is used as index
> [0] to map the interrupt in the GIC.
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?h=next-20220720#n291

Using the SPI number sounds strange to me, as the consumer
(Ethernet PHY) is linked to the IRQC, not to the GIC directly.

> > "The first cell should contain external interrupt number (IRQ0-7)"
> >
> Probably I need to reword this to "The first cell should contain the
> SPI number for IRQ0-7/NMI interrupt lines" ?

Oh, so zero is the NMI?
And 1-8 are IRQ0-7.

All of this should be documented in the bindings.

Probably you want to document the parent interrupts:
  - First entry is NMI,
  - Next 8 entries are IRQ0-7,
  - Next 32 entries are TINT0-31.
Currently it's a flat list.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds