linux-kernel - Re: [PATCH v2 04/21] drm/i915/gt: Only invalidate TLBs exposed to user manipulation

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Message-ID: <YtqQ4dxg2SRVToN3@alfio.lan>
Date:   Fri, 22 Jul 2022 13:58:25 +0200
From:   Andi Shyti <andi.shyti@...ux.intel.com>
To:     Mauro Carvalho Chehab <mchehab@...nel.org>
Cc:     Chris Wilson <chris.p.wilson@...el.com>,
        Daniel Vetter <daniel@...ll.ch>,
        Dave Airlie <airlied@...hat.com>,
        David Airlie <airlied@...ux.ie>,
        Jani Nikula <jani.nikula@...ux.intel.com>,
        Joonas Lahtinen <joonas.lahtinen@...ux.intel.com>,
        Rodrigo Vivi <rodrigo.vivi@...el.com>,
        Tvrtko Ursulin <tvrtko.ursulin@...ux.intel.com>,
        dri-devel@...ts.freedesktop.org, intel-gfx@...ts.freedesktop.org,
        linux-kernel@...r.kernel.org, stable@...r.kernel.org,
        Fei Yang <fei.yang@...el.com>,
        Andi Shyti <andi.shyti@...ux.intel.com>,
        Thomas Hellström 
        <thomas.hellstrom@...ux.intel.com>
Subject: Re: [PATCH v2 04/21] drm/i915/gt: Only invalidate TLBs exposed to
 user manipulation

Hi Mauro,

On Thu, Jul 14, 2022 at 01:06:09PM +0100, Mauro Carvalho Chehab wrote:
> From: Chris Wilson <chris.p.wilson@...el.com>
> 
> Don't flush TLBs when the buffer is only used in the GGTT under full
> control of the kernel, as there's no risk of concurrent access
> and stale access from prefetch.
> 
> We only need to invalidate the TLB if they are accessible by the user.
> That helps to reduce the performance regression introduced by TLB
> invalidate logic.
> 
> Cc: stable@...r.kernel.org
> Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
> Signed-off-by: Chris Wilson <chris.p.wilson@...el.com>
> Cc: Fei Yang <fei.yang@...el.com>
> Cc: Andi Shyti <andi.shyti@...ux.intel.com>
> Acked-by: Thomas Hellström <thomas.hellstrom@...ux.intel.com>
> Signed-off-by: Mauro Carvalho Chehab <mchehab@...nel.org>

Please, once you have sorted out Tvrtko's question you can add:

Reviewed-by: Andi Shyti <andi.shyti@...ux.intel.com>

Thanks,
Andi