[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <YtqRSXXiON8Oed96@alfio.lan>
Date: Fri, 22 Jul 2022 14:00:09 +0200
From: Andi Shyti <andi.shyti@...ux.intel.com>
To: Mauro Carvalho Chehab <mchehab@...nel.org>
Cc: Chris Wilson <chris.p.wilson@...el.com>,
Andi Shyti <andi.shyti@...ux.intel.com>,
Daniel Vetter <daniel@...ll.ch>,
Daniele Ceraolo Spurio <daniele.ceraolospurio@...el.com>,
Dave Airlie <airlied@...hat.com>,
David Airlie <airlied@...ux.ie>,
Jani Nikula <jani.nikula@...ux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@...ux.intel.com>,
Lucas De Marchi <lucas.demarchi@...el.com>,
Matt Roper <matthew.d.roper@...el.com>,
Rodrigo Vivi <rodrigo.vivi@...el.com>,
Tvrtko Ursulin <tvrtko.ursulin@...ux.intel.com>,
dri-devel@...ts.freedesktop.org, intel-gfx@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, stable@...r.kernel.org,
Fei Yang <fei.yang@...el.com>,
Thomas Hellström
<thomas.hellstrom@...ux.intel.com>
Subject: Re: [PATCH v2 05/21] drm/i915/gt: Skip TLB invalidations once wedged
Hi Mauro,
On Thu, Jul 14, 2022 at 01:06:10PM +0100, Mauro Carvalho Chehab wrote:
> From: Chris Wilson <chris.p.wilson@...el.com>
>
> Skip all further TLB invalidations once the device is wedged and
> had been reset, as, on such cases, it can no longer process instructions
> on the GPU and the user no longer has access to the TLB's in each engine.
>
> That helps to reduce the performance regression introduced by TLB
> invalidate logic.
>
> Cc: stable@...r.kernel.org
> Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
> Signed-off-by: Chris Wilson <chris.p.wilson@...el.com>
> Cc: Fei Yang <fei.yang@...el.com>
> Cc: Andi Shyti <andi.shyti@...ux.intel.com>
> Acked-by: Thomas Hellström <thomas.hellstrom@...ux.intel.com>
> Signed-off-by: Mauro Carvalho Chehab <mchehab@...nel.org>
I haven't read any concern from Tvrtko here, in any case:
Reviewed-by: Andi Shyti <andi.shyti@...ux.intel.com>
thanks,
Andi
Powered by blists - more mailing lists