linux-kernel - Re: [PATCH] KVM: SVM: Do not virtualize MSR accesses for APIC LVTT register

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Message-ID: <4d03f8b0-723c-7ac5-5078-95330e888e60@redhat.com>
Date:   Mon, 25 Jul 2022 11:46:32 +0200
From:   Paolo Bonzini <pbonzini@...hat.com>
To:     Suravee Suthikulpanit <suravee.suthikulpanit@....com>,
        linux-kernel@...r.kernel.org, kvm@...r.kernel.org
Cc:     mlevitsk@...hat.com, seanjc@...gle.com, jon.grimm@....com
Subject: Re: [PATCH] KVM: SVM: Do not virtualize MSR accesses for APIC LVTT
 register

On 7/25/22 05:34, Suravee Suthikulpanit wrote:
> AMD does not support APIC TSC-deadline timer mode. AVIC hardware
> will generate GP fault when guest kernel writes 1 to bits [18]
> of the APIC LVTT register (offset 0x32) to set the timer mode.
> (Note: bit 18 is reserved on AMD system).
> 
> Therefore, always intercept and let KVM emulate the MSR accesses.
> 
> Fixes: f3d7c8aa6882 ("KVM: SVM: Fix x2APIC MSRs interception")
> Signed-off-by: Suravee Suthikulpanit<suravee.suthikulpanit@....com>

Does this fix some kvm-unit-tests testcase?

Anyway, I queued the patch, thanks!

Paolo