linux-kernel - Re: [PATCH] KVM: SVM: Do not virtualize MSR accesses for APIC LVTT register

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Message-ID: <dd494ece-06c7-0330-7ab8-e0c736532d50@amd.com>
Date:   Mon, 25 Jul 2022 19:46:12 +0700
From:   Suravee Suthikulpanit <suravee.suthikulpanit@....com>
To:     Paolo Bonzini <pbonzini@...hat.com>, linux-kernel@...r.kernel.org,
        kvm@...r.kernel.org
Cc:     mlevitsk@...hat.com, seanjc@...gle.com, jon.grimm@....com
Subject: Re: [PATCH] KVM: SVM: Do not virtualize MSR accesses for APIC LVTT
 register



On 7/25/22 4:46 PM, Paolo Bonzini wrote:
> On 7/25/22 05:34, Suravee Suthikulpanit wrote:
>> AMD does not support APIC TSC-deadline timer mode. AVIC hardware
>> will generate GP fault when guest kernel writes 1 to bits [18]
>> of the APIC LVTT register (offset 0x32) to set the timer mode.
>> (Note: bit 18 is reserved on AMD system).
>>
>> Therefore, always intercept and let KVM emulate the MSR accesses.
>>
>> Fixes: f3d7c8aa6882 ("KVM: SVM: Fix x2APIC MSRs interception")
>> Signed-off-by: Suravee Suthikulpanit<suravee.suthikulpanit@....com>
> 
> Does this fix some kvm-unit-tests testcase?

I am not sure if we have kvm-unit-tests testcases for this.
I found this when enabling tsc-deadline option in QEMU causing
the vm to fail to boot.

> Anyway, I queued the patch, thanks!
> 
> Paolo

Thank you,
Suravee