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Message-Id: <20220725131521.607904-2-robert.marko@sartura.hr>
Date: Mon, 25 Jul 2022 15:15:21 +0200
From: Robert Marko <robert.marko@...tura.hr>
To: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
lars.povlsen@...rochip.com, Steen.Hegelund@...rochip.com,
UNGLinuxDriver@...rochip.com, arnd@...db.de,
alexandre.belloni@...tlin.com, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc: Robert Marko <robert.marko@...tura.hr>
Subject: [PATCH 2/2] arm64: dts: microchip: sparx5: dont use PSCI for core bringup
As described in previous commit, PSCI is not implemented on this SoC at
all, so use spin-tables to bringup the cores.
Tested on PCB134 with eMMC (VSC5640EV).
Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support")
Signed-off-by: Robert Marko <robert.marko@...tura.hr>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 38da24c1796c..ea2b07ca2887 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -40,14 +40,16 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x0>;
- enable-method = "psci";
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x0000fff8>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x1>;
- enable-method = "psci";
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x0000fff8>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
--
2.37.1
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