Message-ID: <CAOnJCULXZ1DXXsY=s+eMhqvmdwHvnurHT-Ozhq6UDd5AX0hHsA@mail.gmail.com>
Date:   Tue, 26 Jul 2022 01:10:10 -0700
From:   Atish Patra <atishp@...shpatra.org>
To:     Conor Dooley <mail@...chuod.ie>
Cc:     Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Palmer Dabbelt <palmer@...osinc.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Sudeep Holla <sudeep.holla@....com>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        "Rafael J . Wysocki" <rafael@...nel.org>,
        Daire McNamara <daire.mcnamara@...rochip.com>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Niklas Cassel <niklas.cassel@....com>,
        Damien Le Moal <damien.lemoal@...nsource.wdc.com>,
        Geert Uytterhoeven <geert@...ux-m68k.org>,
        Zong Li <zong.li@...ive.com>,
        Emil Renner Berthing <kernel@...il.dk>,
        Jonas Hahnfeld <hahnjo@...njo.de>, Guo Ren <guoren@...nel.org>,
        Anup Patel <anup@...infault.org>,
        Heiko Stuebner <heiko@...ech.de>,
        Philipp Tomsich <philipp.tomsich@...ll.eu>,
        Rob Herring <robh@...nel.org>, Marc Zyngier <maz@...nel.org>,
        Viresh Kumar <viresh.kumar@...aro.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        Brice Goglin <Brice.Goglin@...ia.fr>
Subject: Re: [PATCH v4 1/2] arm64: topology: move store_cpu_topology() to
 shared code

On Fri, Jul 15, 2022 at 10:53 AM Conor Dooley <mail@...chuod.ie> wrote:
>
> From: Conor Dooley <conor.dooley@...rochip.com>
>
> arm64's method of defining a default cpu topology requires only minimal
> changes to apply to RISC-V also. The current arm64 implementation exits
> early in a uniprocessor configuration by reading MPIDR & claiming that
> uniprocessor can rely on the default values.
>
> This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64:
> topology: Stop using MPIDR for topology information")', because the
> current code just assigns default values for multiprocessor systems.
>
> With the MPIDR references removed, store_cpu_topolgy() can be moved to
> the common arch_topology code.
>
> CC: stable@...r.kernel.org
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> Reviewed-by: Sudeep Holla <sudeep.holla@....com>
> ---
>  arch/arm64/kernel/topology.c | 40 ------------------------------------
>  drivers/base/arch_topology.c | 19 +++++++++++++++++
>  2 files changed, 19 insertions(+), 40 deletions(-)
>
> diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
> index 869ffc4d4484..7889a00f5487 100644
> --- a/arch/arm64/kernel/topology.c
> +++ b/arch/arm64/kernel/topology.c
> @@ -22,46 +22,6 @@
>  #include <asm/cputype.h>
>  #include <asm/topology.h>
>
> -void store_cpu_topology(unsigned int cpuid)
> -{
> -       struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];
> -       u64 mpidr;
> -
> -       if (cpuid_topo->package_id != -1)
> -               goto topology_populated;
> -
> -       mpidr = read_cpuid_mpidr();
> -
> -       /* Uniprocessor systems can rely on default topology values */
> -       if (mpidr & MPIDR_UP_BITMASK)
> -               return;
> -
> -       /*
> -        * This would be the place to create cpu topology based on MPIDR.
> -        *
> -        * However, it cannot be trusted to depict the actual topology; some
> -        * pieces of the architecture enforce an artificial cap on Aff0 values
> -        * (e.g. GICv3's ICC_SGI1R_EL1 limits it to 15), leading to an
> -        * artificial cycling of Aff1, Aff2 and Aff3 values. IOW, these end up
> -        * having absolutely no relationship to the actual underlying system
> -        * topology, and cannot be reasonably used as core / package ID.
> -        *
> -        * If the MT bit is set, Aff0 *could* be used to define a thread ID, but
> -        * we still wouldn't be able to obtain a sane core ID. This means we
> -        * need to entirely ignore MPIDR for any topology deduction.
> -        */
> -       cpuid_topo->thread_id  = -1;
> -       cpuid_topo->core_id    = cpuid;
> -       cpuid_topo->package_id = cpu_to_node(cpuid);
> -
> -       pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n",
> -                cpuid, cpuid_topo->package_id, cpuid_topo->core_id,
> -                cpuid_topo->thread_id, mpidr);
> -
> -topology_populated:
> -       update_siblings_masks(cpuid);
> -}
> -
>  #ifdef CONFIG_ACPI
>  static bool __init acpi_cpu_is_threaded(int cpu)
>  {
> diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
> index 0424b59b695e..0e2c6b30dd69 100644
> --- a/drivers/base/arch_topology.c
> +++ b/drivers/base/arch_topology.c
> @@ -841,4 +841,23 @@ void __init init_cpu_topology(void)
>                 return;
>         }
>  }
> +
> +void store_cpu_topology(unsigned int cpuid)
> +{
> +       struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];
> +
> +       if (cpuid_topo->package_id != -1)
> +               goto topology_populated;
> +
> +       cpuid_topo->thread_id = -1;
> +       cpuid_topo->core_id = cpuid;
> +       cpuid_topo->package_id = cpu_to_node(cpuid);
> +
> +       pr_debug("CPU%u: package %d core %d thread %d\n",
> +                cpuid, cpuid_topo->package_id, cpuid_topo->core_id,
> +                cpuid_topo->thread_id);
> +
> +topology_populated:
> +       update_siblings_masks(cpuid);
> +}
>  #endif
> --
> 2.37.1
>

LGTM.
Reviewed-by: Atish Patra <atishp@...osinc.com>



--
Regards,
Atish

Powered by blists - more mailing lists