linux-kernel - Re: [PATCH] RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <CAAhSdy0XwTsQ+dgYatqf6BvGmcGwz_bzmdV5fNeF8oY3rK6dDg@mail.gmail.com>
Date:   Tue, 26 Jul 2022 19:13:52 +0530
From:   Anup Patel <anup@...infault.org>
To:     Conor.Dooley@...rochip.com
Cc:     palmer@...belt.com, apatel@...tanamicro.com, arnd@...db.de,
        paul.walmsley@...ive.com, linux-kernel@...r.kernel.org,
        heinrich.schuchardt@...onical.com, atishp@...shpatra.org,
        linux-riscv@...ts.infradead.org
Subject: Re: [PATCH] RISC-V: Add mvendorid, marchid, and mimpid to
 /proc/cpuinfo output

On Tue, Jul 26, 2022 at 7:10 PM <Conor.Dooley@...rochip.com> wrote:
>
> Hey Anup,
>
> On 26/07/2022 12:57, Anup Patel wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Hi Palmer,
> >
> > On Mon, Jun 20, 2022 at 5:26 PM Anup Patel <apatel@...tanamicro.com> wrote:
> >>
> >> Identifying the underlying RISC-V implementation can be important
> >> for some of the user space applications. For example, the perf tool
> >> uses arch specific CPU implementation id (i.e. CPUID) to select a
> >> JSON file describing custom perf events on a CPU.
> >>
> >> Currently, there is no way to identify RISC-V implementation so we
> >> add mvendorid, marchid, and mimpid to /proc/cpuinfo output.
> >>
> >> Signed-off-by: Anup Patel <apatel@...tanamicro.com>
> >
> > Can this patch be considered for 5.20 ?
>
> iirc I mentioned the consistency of using defined() for
> CONFIG_RISCV_SBI versus IS_ENABLED() elsewhere in arch/riscv/
> but I don't recall a response.

Sorry, I missed your comment. I will address and send v2 soon.

Regards,
Anup

>
> Thanks,
> Conor.