linux-kernel - [PATCH 4/4] ARM: dts: bcmbca: cosmetic change

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Message-Id: <20220729015029.14863-4-william.zhang@broadcom.com>
Date:   Thu, 28 Jul 2022 18:50:29 -0700
From:   William Zhang <william.zhang@...adcom.com>
To:     Linux ARM List <linux-arm-kernel@...ts.infradead.org>
Cc:     Broadcom Kernel List <bcm-kernel-feedback-list@...adcom.com>,
        kursad.oney@...adcom.com, dan.beygelman@...adcom.com,
        f.fainelli@...il.com, anand.gore@...adcom.com,
        joel.peshkin@...adcom.com,
        William Zhang <william.zhang@...adcom.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH 4/4] ARM: dts: bcmbca: cosmetic change

Add new line between dts nodes for BCM63178 and BCM6878.

Signed-off-by: William Zhang <william.zhang@...adcom.com>

---

 arch/arm/boot/dts/bcm63178.dtsi | 3 +++
 arch/arm/boot/dts/bcm6878.dtsi  | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi
index dba71fa53466..29e621517e06 100644
--- a/arch/arm/boot/dts/bcm63178.dtsi
+++ b/arch/arm/boot/dts/bcm63178.dtsi
@@ -32,6 +32,7 @@ CA7_1: cpu@1 {
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
 		};
+
 		CA7_2: cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
@@ -39,6 +40,7 @@ CA7_2: cpu@2 {
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
 		};
+
 		L2_0: l2-cache0 {
 			compatible = "cache";
 		};
@@ -68,6 +70,7 @@ periph_clk: periph-clk {
 			#clock-cells = <0>;
 			clock-frequency = <200000000>;
 		};
+
 		uart_clk: uart-clk {
 			compatible = "fixed-factor-clock";
 			#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi
index 6dd3d2df4e16..e89a19b31dc9 100644
--- a/arch/arm/boot/dts/bcm6878.dtsi
+++ b/arch/arm/boot/dts/bcm6878.dtsi
@@ -32,6 +32,7 @@ CA7_1: cpu@1 {
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
 		};
+
 		L2_0: l2-cache0 {
 			compatible = "cache";
 		};
@@ -59,6 +60,7 @@ periph_clk: periph-clk {
 			#clock-cells = <0>;
 			clock-frequency = <200000000>;
 		};
+
 		uart_clk: uart-clk {
 			compatible = "fixed-factor-clock";
 			#clock-cells = <0>;
-- 
2.34.1


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