lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20220802070518.855951-2-nagasuresh.relli@microchip.com>
Date:   Tue, 2 Aug 2022 12:35:16 +0530
From:   Naga Sureshkumar Relli <nagasuresh.relli@...rochip.com>
To:     <broonie@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor.dooley@...rochip.com>
CC:     <linux-spi@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        Naga Sureshkumar Relli <nagasuresh.relli@...rochip.com>
Subject: [PATCH v2 1/3] spi: dt-binding: add Microchip CoreQSPI compatible

Add compatible string for Microchip CoreQSPI controller.

Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@...rochip.com>
---
 .../devicetree/bindings/spi/microchip,mpfs-spi.yaml  | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
index 7326c0a28d16..8d252eb8c460 100644
--- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -14,9 +14,15 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - microchip,mpfs-spi
-      - microchip,mpfs-qspi
+    oneOf:
+      - description: Microchip's Polarfire SoC QSPI controller.
+        items:
+          - const: microchip,mpfs-qspi
+          - const: microchip,coreqspi-rtl-v2
+      - description: Microchip's fabric based QSPI IP core
+        const: microchip,coreqspi-rtl-v2
+      - description: Microchip's Polarfire SoC SPI controller.
+        const: microchip,mpfs-spi
 
   reg:
     maxItems: 1
-- 
2.25.1

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ