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Message-ID: <CAH_iE_3s9=-Lk7bk993==jJz0m8pp+GEzUZvDoH4MR_SSSCr-A@mail.gmail.com>
Date: Tue, 2 Aug 2022 17:40:43 +0530
From: naga sureshkumar <nagasuresh12@...il.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc: Naga Sureshkumar Relli <nagasuresh.relli@...rochip.com>,
broonie@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor.dooley@...rochip.com,
linux-spi@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/3] spi: dt-binding: add Microchip CoreQSPI compatible
Hi Krzysztof,
Thanks for the review.
On Tue, Aug 2, 2022 at 3:55 PM Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org> wrote:
>
> On 02/08/2022 09:05, Naga Sureshkumar Relli wrote:
> > Add compatible string for Microchip CoreQSPI controller.
> >
> > Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@...rochip.com>
> > ---
> > .../devicetree/bindings/spi/microchip,mpfs-spi.yaml | 12 +++++++++---
> > 1 file changed, 9 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> > index 7326c0a28d16..8d252eb8c460 100644
> > --- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> > +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> > @@ -14,9 +14,15 @@ allOf:
> >
> > properties:
> > compatible:
> > - enum:
> > - - microchip,mpfs-spi
> > - - microchip,mpfs-qspi
> > + oneOf:
> > + - description: Microchip's Polarfire SoC QSPI controller.
> > + items:
> > + - const: microchip,mpfs-qspi
> > + - const: microchip,coreqspi-rtl-v2
>
> This is a bit confusing and it is no described in commit msg. You change
> compatibles for existing binding. This must be a separate commit with
> its own explanation/reasoning.
Ok I will split it and add information in the commit msg.
Thanks,
Naga Sureshkumar Relli.
>
>
> Best regards,
> Krzysztof
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