linux-kernel - Re: [PATCH 0/5] clk/qcom: Support gdsc collapse polling using 'reset' inteface

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Message-ID: <0f90ef4d-4b74-2746-a37c-4a661cc0d5ea@quicinc.com>
Date:   Wed, 3 Aug 2022 15:31:48 +0530
From:   Akhil P Oommen <quic_akhilpo@...cinc.com>
To:     Rob Clark <robdclark@...il.com>,
        Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC:     freedreno <freedreno@...ts.freedesktop.org>,
        <dri-devel@...ts.freedesktop.org>, <linux-arm-msm@...r.kernel.org>,
        "Bjorn Andersson" <bjorn.andersson@...aro.org>,
        Stephen Boyd <swboyd@...omium.org>,
        Douglas Anderson <dianders@...omium.org>,
        Andy Gross <agross@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...ainline.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Michael Turquette <mturquette@...libre.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        "Rob Herring" <robh+dt@...nel.org>,
        Stephen Boyd <sboyd@...nel.org>, <devicetree@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 0/5] clk/qcom: Support gdsc collapse polling using 'reset'
 inteface

On 8/3/2022 12:02 AM, Rob Clark wrote:
> On Tue, Aug 2, 2022 at 12:02 AM Dmitry Baryshkov
> <dmitry.baryshkov@...aro.org> wrote:
>> On 30/07/2022 12:17, Akhil P Oommen wrote:
>>> Some clients like adreno gpu driver would like to ensure that its gdsc
>>> is collapsed at hardware during a gpu reset sequence. This is because it
>>> has a votable gdsc which could be ON due to a vote from another subsystem
>>> like tz, hyp etc or due to an internal hardware signal.
>> If this is votable, do we have any guarantee that the gdsc will collapse
>> at all? How can we proceed if it did not collapse?
> Other potential votes should be transient.  But I guess we eventually
> need to timeout and give up.  At which point we are no worse off than
> before.
>
> But hmm, we aren't using RBBM_SW_RESET_CMD for sw reset like we have
> on previous generations?  That does seem a bit odd.  Looks like kgsl
> does use it.
>
> BR,
> -R
Like Rob mentioned there could be transient votes from other 
clients/subsystem. It could be even stuck ON when hardware is in bad 
shape in some very rare cases. For the worst case scenario, I have added 
a timeout (500msec) in the gdsc reset op.

I have added the Soft reset in [1]. But this resets only the core gpu 
blocks, not everything. For eg. GMU.

[1] [PATCH v3 7/8] drm/msm/a6xx: Improve gpu recovery sequence

>
>>> To allow
>>> this, gpucc driver can expose an interface to the client driver using
>>> reset framework. Using this the client driver can trigger a polling within
>>> the gdsc driver.
>> Trigger the polling made me think initially that we will actually
>> trigger something in the HW. Instead the client uses reset framework to
>> poll for the gdsc to be reset.
Yes. I should replace 'trigger' with 'start' here.

-Akhil.
>>
>>> This series is rebased on top of linus's master branch.
>>>
>>> Related discussion: https://patchwork.freedesktop.org/patch/493144/
>>>
>>>
>>> Akhil P Oommen (5):
>>>     dt-bindings: clk: qcom: Support gpu cx gdsc reset
>>>     clk: qcom: Allow custom reset ops
>>>     clk: qcom: gpucc-sc7280: Add cx collapse reset support
>>>     clk: qcom: gdsc: Add a reset op to poll gdsc collapse
>>>     arm64: dts: qcom: sc7280: Add Reset support for gpu
>>>
>>>    arch/arm64/boot/dts/qcom/sc7280.dtsi          |  3 +++
>>>    drivers/clk/qcom/gdsc.c                       | 23 +++++++++++++++++++----
>>>    drivers/clk/qcom/gdsc.h                       |  7 +++++++
>>>    drivers/clk/qcom/gpucc-sc7280.c               |  6 ++++++
>>>    drivers/clk/qcom/reset.c                      |  6 ++++++
>>>    drivers/clk/qcom/reset.h                      |  2 ++
>>>    include/dt-bindings/clock/qcom,gpucc-sc7280.h |  3 +++
>>>    7 files changed, 46 insertions(+), 4 deletions(-)
>>>
>>
>> --
>> With best wishes
>> Dmitry