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Message-ID: <CA+V-a8utnf6EBCia5zNcLHgpJikWcB3csT=82EV_ekSse6xyQg@mail.gmail.com>
Date: Wed, 3 Aug 2022 14:37:37 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Jacopo Mondi <jacopo@...ndi.org>,
Niklas Söderlund <niklas.soderlund@...natech.se>,
Sakari Ailus <sakari.ailus@...ux.intel.com>,
Hans Verkuil <hverkuil-cisco@...all.nl>,
Geert Uytterhoeven <geert+renesas@...der.be>,
linux-media <linux-media@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
LKML <linux-kernel@...r.kernel.org>,
Biju Das <biju.das.jz@...renesas.com>
Subject: Re: [PATCH 2/4] media: dt-bindings: media: Document RZ/G2L CRU
Hi Krzysztof,
Thank you for the review.
On Tue, Aug 2, 2022 at 8:37 AM Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org> wrote:
>
> On 01/08/2022 23:47, Lad Prabhakar wrote:
> > Document the CRU block found on Renesas RZ/G2L SoC's.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > ---
> > RFC v2 -> v1
> > * Dropped endpoint stuff from port1 as suggested by Rob
> > * Updated description for endpoint
> >
> > RFC v1 -> RFC v2
> > * Dropped CSI
> > ---
> > .../bindings/media/renesas,rzg2l-cru.yaml | 142 ++++++++++++++++++
> > 1 file changed, 142 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
> > new file mode 100644
> > index 000000000000..d7389693dae9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
> > @@ -0,0 +1,142 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +# Copyright (C) 2022 Renesas Electronics Corp.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing
> > +
> > +maintainers:
> > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > +
> > +description:
> > + The CRU image processing module is a data conversion module equipped with pixel
> > + color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and
> > + parallel (including ITU-R BT.656) input are provided as the image sensor interface.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
>
> No need for oneOf, unless you already have a patch adding second case to
> oneOf.
>
Agreed, I will drop that.
> > + - items:
> > + - enum:
> > + - renesas,r9a07g044-cru # RZ/G2{L,LC}
> > + - renesas,r9a07g054-cru # RZ/V2L
> > + - const: renesas,rzg2l-cru
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 3
> > +
> > + interrupt-names:
> > + items:
> > + - const: image_conv
> > + - const: image_conv_err
> > + - const: axi_mst_err
> > +
> > + clocks:
> > + items:
> > + - description: CRU Main clock
> > + - description: CPU Register access clock
> > + - description: CRU image transfer clock
> > +
> > + clock-names:
> > + items:
> > + - const: vclk
> > + - const: pclk
> > + - const: aclk
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + resets:
> > + items:
> > + - description: CRU_PRESETN reset terminal
> > + - description: CRU_ARESETN reset terminal
> > +
> > + reset-names:
> > + items:
> > + - const: presetn
> > + - const: aresetn
> > +
> > + ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > +
> > + properties:
> > + port@0:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
> > + unevaluatedProperties: false
> > + description:
> > + Input port node, single endpoint describing a parallel input source.
> > +
> > + properties:
> > + endpoint:
> > + $ref: video-interfaces.yaml#
> > + unevaluatedProperties: false
> > +
> > + properties:
> > + hsync-active: true
> > + vsync-active: true
> > + bus-width: true
> > + data-shift: true
> > +
> > + port@1:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description:
> > + Input port node, describing the Image Processing module connected to the
> > + CSI-2 receiver.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - interrupt-names
> > + - clocks
> > + - clock-names
> > + - resets
> > + - reset-names
> > + - power-domains
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + # Device node example with CSI-2
> > + - |
> > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + cru: video@...30000 {
> > + compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru";
>
> Also 4-space for DTS example, please.
>
Agreed.
Cheers,
Prabhakar
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