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Message-ID: <Yuqy8wJyHASPdIBG@sirena.org.uk>
Date:   Wed, 3 Aug 2022 18:40:03 +0100
From:   Mark Brown <broonie@...nel.org>
To:     Sudip Mukherjee <sudip.mukherjee@...ive.com>
Cc:     Serge Semin <fancer.lancer@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Greentime Hu <greentime.hu@...ive.com>,
        Jude Onyenegecha <jude.onyenegecha@...ive.com>,
        William Salmon <william.salmon@...ive.com>,
        Adnan Chowdhury <adnan.chowdhury@...ive.com>,
        Ben Dooks <ben.dooks@...ive.com>, linux-spi@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Jeegar Lakhani <jeegar.lakhani@...ive.com>
Subject: Re: [PATCH 01/11] spi: dw: define capability for enhanced spi

On Wed, Aug 03, 2022 at 06:34:53PM +0100, Sudip Mukherjee wrote:
> On Tue, Aug 2, 2022 at 7:48 PM Mark Brown <broonie@...nel.org> wrote:
> > On Tue, Aug 02, 2022 at 06:57:45PM +0100, Sudip Mukherjee wrote:

> > > +#define DW_SPI_CAP_EXT_SPI           BIT(2)

> > This isn't at all descriptive, it'd be better to have a capability bit
> > for the various multi-line data modes (or possibly individual bits for
> > them, though board setup will stop us using things that aren't supported
> > in a given design anyway so it's a bit redundant) - that'd be a lot
> > clearer and avoid confusion further down the line when some other
> > feature gets added.

> Do you mean to add separate capability bit like:
> DW_SPI_CAP_DUAL_SPI
> DW_SPI_CAP_QUAD_SPI and
> DW_SPI_CAP_OCTAL_SPI ?

Either that or some rolled together capability with an at least somewhat
descriptive name.

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