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Message-ID: <dc4059db-ab72-905e-0f04-1c86cbd3d49a@microchip.com>
Date: Fri, 5 Aug 2022 09:14:55 +0000
From: <Conor.Dooley@...rochip.com>
To: <Nagasuresh.Relli@...rochip.com>, <broonie@...nel.org>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>
CC: <linux-spi@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<Valentina.FernandezAlanis@...rochip.com>
Subject: Re: [PATCH v3 0/4] Add support for Microchip QSPI controller
On 05/08/2022 06:30, Naga Sureshkumar Relli wrote:
> This patch enables the Microchip's FPGA QSPI and Polarfire SoC QSPI
> controller support.
>
> Tested spi-nand (W25N01GV) and spi-nor (MT25QL256A) on Microchip's
> ICICLE kit. tested using both FPGA QSPI and Polarfie SoC QSPI.
Pending Krzysztof's requests etc:
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
@Valentina could you test this version please?
Thanks,
Conor.
>
> changes in v3
> ------------
> 1. Added dev_err_probe() at places like probe failures
> 2. Split the dt-bindings one for adding coreqspi compatible
> and other one to add coreqspi as fallback to mpfs-qspi.
>
> changes in v2
> ------------
> 1. Replaced spi_alloc_master() with devm_spi_alloc_master()
> 2. Used dev_err_probe() when devm_spi_alloc_master() fails.
> 3. Added shared IRQ flag in the interrupt registration.
> 4. Updated the dt_bindings so that there is a differentiation
> between FPGA QSPI IP core and hard QSPI IP core.
>
> Naga Sureshkumar Relli (4):
> spi: dt-binding: document microchip coreQSPI
> spi: dt-binding: add coreqspi as a fallback for mpfs-qspi
> spi: microchip-core-qspi: Add support for microchip fpga qspi
> controllers
> MAINTAINERS: add qspi to Polarfire SoC entry
>
> .../bindings/spi/microchip,mpfs-spi.yaml | 15 +-
> MAINTAINERS | 1 +
> drivers/spi/Kconfig | 9 +
> drivers/spi/Makefile | 1 +
> drivers/spi/spi-microchip-core-qspi.c | 601 ++++++++++++++++++
> 5 files changed, 623 insertions(+), 4 deletions(-)
> create mode 100644 drivers/spi/spi-microchip-core-qspi.c
>
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