linux-kernel - Re: [PATCH v3 4/4] MAINTAINERS: add qspi to Polarfire SoC entry

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Message-ID: <4054682e-fc97-377f-9ebf-da99d2f3ec5c@microchip.com>
Date:   Fri, 5 Aug 2022 12:07:57 +0000
From:   <Conor.Dooley@...rochip.com>
To:     <broonie@...nel.org>, <Nagasuresh.Relli@...rochip.com>
CC:     <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
        <Conor.Dooley@...rochip.com>, <linux-spi@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <Valentina.FernandezAlanis@...rochip.com>
Subject: Re: [PATCH v3 4/4] MAINTAINERS: add qspi to Polarfire SoC entry

On 05/08/2022 12:05, Mark Brown wrote:
> On Fri, Aug 05, 2022 at 11:00:19AM +0530, Naga Sureshkumar Relli wrote:
>> Add the qspi driver to existing Polarfire SoC entry.
> 
>> +++ b/MAINTAINERS
>> @@ -17146,6 +17146,7 @@ S:	Supported
>>   F:	arch/riscv/boot/dts/microchip/
>>   F:	drivers/mailbox/mailbox-mpfs.c
>>   F:	drivers/soc/microchip/
>> +F:	drivers/spi/spi-microchip-core-qspi.c
>>   F:	drivers/spi/spi-microchip-core.c
>>   F:	include/soc/microchip/mpfs.h
> 
> You should also add a pattern for the DT binding here.

All of the bindings for the platform should have entries then
right? I'll send a separate patch adding all of the missing
bindings. I have a deferred change to the entry that needs to
be sent to Arnd anyway so I can queue the two together.
Nothing to be gained by waiting until this driver lands in 6.1+
to have MAINTAINERS coverage of the bindings :)

Thanks,
Conor.