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Message-ID: <20220811162307.1384962-1-hamza.mahfooz@amd.com>
Date: Thu, 11 Aug 2022 12:23:07 -0400
From: Hamza Mahfooz <hamza.mahfooz@....com>
To: <linux-kernel@...r.kernel.org>
CC: Hamza Mahfooz <hamza.mahfooz@....com>,
Anders Roxell <anders.roxell@...aro.org>,
Harry Wentland <harry.wentland@....com>,
Leo Li <sunpeng.li@....com>,
Rodrigo Siqueira <Rodrigo.Siqueira@....com>,
"Alex Deucher" <alexander.deucher@....com>,
Christian König <christian.koenig@....com>,
"Pan, Xinhui" <Xinhui.Pan@....com>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
hersen wu <hersenxs.wu@....com>, Wayne Lin <Wayne.Lin@....com>,
Fangzhi Zuo <Jerry.Zuo@....com>,
Nicholas Kazlauskas <nicholas.kazlauskas@....com>,
"Roman Li" <Roman.Li@....com>, <amd-gfx@...ts.freedesktop.org>,
<dri-devel@...ts.freedesktop.org>
Subject: [PATCH] drm/amd/display: fix DSC related non-x86/PPC64 compilation issue
Need to protect DSC code with CONFIG_DRM_AMD_DC_DCN.
Fixes the following build errors on arm64:
ERROR: modpost: "dc_dsc_get_policy_for_timing" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "dc_dsc_compute_bandwidth_range" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
Fixes: 0087990a9f57 ("drm/amd/display: consider DSC pass-through during mode validation")
Reported-by: Anders Roxell <anders.roxell@...aro.org>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@....com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index ef6c94cd852b..0c52c0867211 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1387,8 +1387,6 @@ bool pre_validate_dsc(struct drm_atomic_state *state,
return (ret == 0);
}
-#endif
-
static unsigned int kbps_from_pbn(unsigned int pbn)
{
unsigned int kbps = pbn;
@@ -1416,6 +1414,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16;
}
+#endif /* CONFIG_DRM_AMD_DC_DCN */
enum dc_status dm_dp_mst_is_port_support_mode(
struct amdgpu_dm_connector *aconnector,
@@ -1428,6 +1427,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
struct dc_dsc_bw_range bw_range = {0};
int bpp, pbn, branch_max_throughput_mps = 0;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
/*
* check if the mode could be supported if DSC pass-through is supported
* AND check if there enough bandwidth available to support the mode
@@ -1461,13 +1461,16 @@ enum dc_status dm_dp_mst_is_port_support_mode(
return DC_FAIL_BANDWIDTH_VALIDATE;
}
} else {
+#endif
/* check if mode could be supported within full_pbn */
bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
if (pbn > aconnector->port->full_pbn)
return DC_FAIL_BANDWIDTH_VALIDATE;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
}
+#endif
/* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
switch (stream->timing.pixel_encoding) {
--
2.37.1
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