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Message-ID: <ca555430-055c-debb-fdb4-fa7f78129780@microchip.com>
Date: Mon, 15 Aug 2022 18:52:50 +0000
From: <Conor.Dooley@...rochip.com>
To: <prabhakar.mahadev-lad.rj@...renesas.com>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <paul.walmsley@...ive.com>,
<palmer@...belt.com>, <aou@...s.berkeley.edu>,
<geert+renesas@...der.be>
CC: <anup@...infault.org>, <linux-renesas-soc@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <prabhakar.csengg@...il.com>,
<biju.das.jz@...renesas.com>
Subject: Re: [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five
SoC
On 15/08/2022 16:14, Lad Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> upstream kernel to boot on RZ/Five SMARC EVK board.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> v1->v2
> * New patch
> ---
> arch/riscv/configs/defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index aed332a9d4ea..de0ccf816c08 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -26,6 +26,7 @@ CONFIG_EXPERT=y
> # CONFIG_SYSFS_SYSCALL is not set
> CONFIG_PROFILING=y
> CONFIG_SOC_MICROCHIP_POLARFIRE=y
> +CONFIG_SOC_RENESAS_RZFIVE=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_STARFIVE=y
> CONFIG_SOC_VIRT=y
> @@ -123,6 +124,7 @@ CONFIG_INPUT_MOUSEDEV=y
> CONFIG_SERIAL_8250=y
> CONFIG_SERIAL_8250_CONSOLE=y
> CONFIG_SERIAL_OF_PLATFORM=y
> +CONFIG_SERIAL_SH_SCI=y
What's this? The patch text makes this look like an accidental
inclusion, but I figure it is required for boot?
Thanks,
Conor.
> CONFIG_VIRTIO_CONSOLE=y
> CONFIG_HW_RANDOM=y
> CONFIG_HW_RANDOM_VIRTIO=y
> --
> 2.25.1
>
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