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Message-ID: <dd9d439d-06a8-b25c-9cea-9065f67a628b@sholland.org>
Date: Mon, 15 Aug 2022 19:16:37 -0500
From: Samuel Holland <samuel@...lland.org>
To: Icenowy Zheng <uwu@...nowy.me>,
Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-sunxi@...ts.linux.dev
Subject: Re: [PATCH 2/4] nvmem: sunxi_sid: Drop the workaround on A64
Hi Icenowy,
On 8/15/22 3:37 AM, Icenowy Zheng wrote:
> 在 2022-08-14星期日的 12:36 -0500,Samuel Holland写道:
>> Now that the SRAM readout code is fixed by using 32-bit accesses, it
>> always returns the same values as register readout, so the A64
>> variant
>> no longer needs the workaround. This makes the D1 variant structure
>> redundant, so remove it.
>
> Is this really tested on A64?
Yes, I tested this on a Pine A64-LTS. You can see the difference easily with
md.{b,w,l,q} in the U-Boot shell.
I verified that all three of the following are identical:
- NVMEM exported to sysfs with the register readout method
- NVMEM exported to sysfs with this patch series applied
- SRAM dump made with md.l in the U-Boot shell
Regards,
Samuel
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