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Message-ID: <b2e13fc0-fb25-de2f-4794-95a0f5b8c878@somainline.org>
Date: Wed, 17 Aug 2022 23:04:07 +0200
From: Konrad Dybcio <konrad.dybcio@...ainline.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Lee Jones <lee@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [RFT PATCH v2 11/14] arm64: dts: qcom: sdm845: switch TCSR mutex
to MMIO
On 17.08.2022 15:03, Krzysztof Kozlowski wrote:
> The TCSR mutex bindings allow device to be described only with address
> space (so it uses MMIO, not syscon regmap). This seems reasonable as
> TCSR mutex is actually a dedicated IO address space and it also fixes DT
> schema checks:
>
> qcom/sdm845-shift-axolotl.dtb: hwlock: 'reg' is a required property
> qcom/sdm845-shift-axolotl.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+'
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> ---
Not tested on a device, but looks good to the eye:
Reviewed-by: Konrad Dybcio <konrad.dybcio@...ainline.org>
Konrad
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 11 +++--------
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 21ed14200986..bd0ec0664283 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -919,12 +919,6 @@ compute-cb@8 {
> };
> };
>
> - tcsr_mutex: hwlock {
> - compatible = "qcom,tcsr-mutex";
> - syscon = <&tcsr_mutex_regs 0 0x1000>;
> - #hwlock-cells = <1>;
> - };
> -
> smp2p-cdsp {
> compatible = "qcom,smp2p";
> qcom,smem = <94>, <432>;
> @@ -2588,9 +2582,10 @@ ipa: ipa@...0000 {
> status = "disabled";
> };
>
> - tcsr_mutex_regs: syscon@...0000 {
> - compatible = "syscon";
> + tcsr_mutex: hwlock@...0000 {
> + compatible = "qcom,tcsr-mutex";
> reg = <0 0x01f40000 0 0x20000>;
> + #hwlock-cells = <1>;
> };
>
> tcsr_regs_1: sycon@...0000 {
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