[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <AS8PR04MB867626BC5C32AA75466BB9E78C6D9@AS8PR04MB8676.eurprd04.prod.outlook.com>
Date: Thu, 18 Aug 2022 10:53:24 +0000
From: Hongxing Zhu <hongxing.zhu@....com>
To: Philipp Zabel <p.zabel@...gutronix.de>,
"l.stach@...gutronix.de" <l.stach@...gutronix.de>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
"robh@...nel.org" <robh@...nel.org>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
"vkoul@...nel.org" <vkoul@...nel.org>,
"alexander.stein@...tq-group.com" <alexander.stein@...tq-group.com>,
"marex@...x.de" <marex@...x.de>
CC: "linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"kernel@...gutronix.de" <kernel@...gutronix.de>,
dl-linux-imx <linux-imx@....com>
Subject: RE: [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST support
> -----Original Message-----
> From: Philipp Zabel <p.zabel@...gutronix.de>
> Sent: 2022年8月18日 16:51
> To: Hongxing Zhu <hongxing.zhu@....com>; l.stach@...gutronix.de;
> bhelgaas@...gle.com; lorenzo.pieralisi@....com; robh@...nel.org;
> shawnguo@...nel.org; vkoul@...nel.org; alexander.stein@...tq-group.com;
> marex@...x.de
> Cc: linux-phy@...ts.infradead.org; devicetree@...r.kernel.org;
> linux-pci@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> linux-kernel@...r.kernel.org; kernel@...gutronix.de; dl-linux-imx
> <linux-imx@....com>
> Subject: Re: [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST
> support
>
> Hi Richard,
>
> On Do, 2022-08-18 at 15:02 +0800, Richard Zhu wrote:
> > On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST
> > bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1.
> > But i.MX8MP has one inversed default value 1b'0 of PERST bit.
> >
> > And the PERST bit should be kept 1b'1 after power and clocks are stable.
> > So add the i.MX8MP PCIe PHY PERST support here.
>
> the description is good now. It would be nice if this could also be mentioned in
> the Reference Manual.
>
> Please replace "add" with "fix" in the subject, as I requested earlier:
> "reset: imx7: Fix i.MX8MP PCIe PHY PERST support".
>
> And add a fixes line:
>
> Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")
>
> With those two changes,
> Reviewed-by: Philipp Zabel <p.zabel@...gutronix.de>
>
Hi Philipp:
Okay, would be changed in next version.
Thanks for your review.
Best Regards
Richard Zhu
> regards
> Philipp
Powered by blists - more mailing lists