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Message-ID: <cc784668-eec9-ff52-1d65-f55efcfae079@microchip.com>
Date: Fri, 19 Aug 2022 13:20:06 +0000
From: <Conor.Dooley@...rochip.com>
To: <krzysztof.kozlowski@...aro.org>, <mturquette@...libre.com>,
<sboyd@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <palmer@...belt.com>,
<Daire.McNamara@...rochip.com>
CC: <paul.walmsley@...ive.com>, <aou@...s.berkeley.edu>,
<linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>
Subject: Re: [PATCH 2/6] dt-bindings: clk: document PolarFire SoC fabric
clocks
On 19/08/2022 13:45, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 19/08/2022 15:22, Conor Dooley wrote:
>> On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the
>> ordinal corners of the chip, which our documentation refers to as
>> "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are
>> highly configurable & many of the input clocks are optional.
>>
>
> Thank you for your patch. There is something to discuss/improve.
>
>> + '#clock-cells':
>> + const: 1
>> + description: |
>> + The clock consumer should specify the desired clock by having the clock
>> + ID in its "clocks" phandle cell.
>> + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
>> + PolarFire clock IDs.
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - '#clock-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + ccc_nw: cccnwclk@...00000 {
>
> Node names should be generic: clock-controller
>
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Further, the label is not required in the example.
I'll fix this for v2, thanks.
Conor.
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