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Message-ID: <20220822192214.GA292150-robh@kernel.org>
Date: Mon, 22 Aug 2022 14:22:14 -0500
From: Rob Herring <robh@...nel.org>
To: Conor Dooley <mail@...chuod.ie>
Cc: linux-kernel@...r.kernel.org,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Daire McNamara <daire.mcnamara@...rochip.com>,
Albert Ou <aou@...s.berkeley.edu>,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
linux-pci@...r.kernel.org, Bjorn Helgaas <bhelgaas@...gle.com>,
Greentime Hu <greentime.hu@...ive.com>,
linux-riscv@...ts.infradead.org,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Palmer Dabbelt <palmer@...belt.com>,
Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v3 3/7] dt-bindings: PCI: microchip,pcie-host: fix
missing dma-ranges
On Sat, 20 Aug 2022 00:14:12 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
>
> The dma-ranges property was missed when adding the binding initially.
> The root port can use up to 6 address translation tables, depending on
> configuration.
>
> Link: https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide # Section 1.3.3
> Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding")
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
> .../devicetree/bindings/pci/microchip,pcie-host.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Rob Herring <robh@...nel.org>
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