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Message-ID: <87v8qhybk8.ffs@tglx>
Date: Wed, 24 Aug 2022 16:13:11 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: Muhammad Usama Anjum <usama.anjum@...labora.com>,
Jonathan Corbet <corbet@....net>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>,
"maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <x86@...nel.org>,
"H. Peter Anvin" <hpa@...or.com>,
"open list:DOCUMENTATION" <linux-doc@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>
Cc: Steven Noonan <steven@...inklabs.net>, usama.anjum@...labora.com,
kernel@...labora.com
Subject: Re: [PATCH 1/3] x86/tsc: implement tsc=directsync for systems
without IA32_TSC_ADJUST
On Mon, Aug 08 2022 at 16:39, Muhammad Usama Anjum wrote:
> From: Steven Noonan <steven@...inklabs.net>
>
> AMD processors don't implement any mechanism like Intel's
> IA32_TSC_ADJUST MSR to sync the TSC. Instead of just relying on the
> BIOS, TSC can be synced by calculating the difference and directly
> writing it to the TSC MSR.
Why? This has been tried before and is known to be flaky and
unrealiable.
> Add directsync flag to turn on the TSC sync when IA32_TSC_MSR isn't
> available. Attempt 1000 times or for 30 seconds before giving up.
Looping 30 seconds with interrupts disabled? Seriously?
Thanks,
tglx
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