linux-kernel - Re: [PATCH v5 12/20] dt-bindings: PCI: dwc: Add dma-coherent property

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Message-ID: <20220831212518.GA277724-robh@kernel.org>
Date:   Wed, 31 Aug 2022 16:25:18 -0500
From:   Rob Herring <robh@...nel.org>
To:     Serge Semin <Sergey.Semin@...kalelectronics.ru>
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Krzysztof Wilczyński <kw@...ux.com>,
        devicetree@...r.kernel.org,
        Pavel Parkhomenko <Pavel.Parkhomenko@...kalelectronics.ru>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Jingoo Han <jingoohan1@...il.com>,
        linux-kernel@...r.kernel.org,
        Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
        Frank Li <Frank.Li@....com>, linux-pci@...r.kernel.org,
        Serge Semin <fancer.lancer@...il.com>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
        Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH v5 12/20] dt-bindings: PCI: dwc: Add dma-coherent property

On Mon, 22 Aug 2022 21:46:53 +0300, Serge Semin wrote:
> DW PCIe EP/RP AXI- and TRGT1-master interfaces are responsible for the
> application memory access. They are used by the RP/EP PCIe buses (MWr/MWr
> TLPs emitted by the peripheral PCIe devices) and the eDMA block. Since all
> of them mainly involve the system memory and basically mean DMA we can
> expect the corresponding platforms can be designed in a way to make sure
> the transactions are cache-coherent. As such the DW PCIe DT-nodes can have
> the 'dma-coherent' property specified. Let's permit it in the DT-bindings
> then.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@...kalelectronics.ru>
> 
> ---
> 
> Changelog v3:
> - This is a new patch created on v3 lap of the series.
> ---
>  Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Reviewed-by: Rob Herring <robh@...nel.org>