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Message-ID: <20220831220614.GA319827-robh@kernel.org>
Date: Wed, 31 Aug 2022 17:06:14 -0500
From: Rob Herring <robh@...nel.org>
To: Dario Binacchi <dario.binacchi@...rulasolutions.com>
Cc: linux-kernel@...r.kernel.org,
Marc Kleine-Budde <mkl@...gutronix.de>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
michael@...rulasolutions.com,
Amarula patchwork <linux-amarula@...rulasolutions.com>,
Vincent Mailhol <mailhol.vincent@...adoo.fr>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Paolo Abeni <pabeni@...hat.com>,
Wolfgang Grandegger <wg@...ndegger.com>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-can@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com, netdev@...r.kernel.org
Subject: Re: [RFC PATCH v3 1/4] dt-bindings: net: can: add STM32 bxcan DT
bindings
On Sun, Aug 28, 2022 at 03:33:26PM +0200, Dario Binacchi wrote:
> Add documentation of device tree bindings for the STM32 basic extended
> CAN (bxcan) controller.
>
> Signed-off-by: Dario Binacchi <dario.binacchi@...rulasolutions.com>
>
> ---
>
> Changes in v3:
> - Remove 'Dario Binacchi <dariobin@...ero.it>' SOB.
> - Add description to the parent of the two child nodes.
> - Move "patterProperties:" after "properties: in top level before "required".
> - Add "clocks" to the "required:" list of the child nodes.
>
> Changes in v2:
> - Change the file name into 'st,stm32-bxcan-core.yaml'.
> - Rename compatibles:
> - st,stm32-bxcan-core -> st,stm32f4-bxcan-core
> - st,stm32-bxcan -> st,stm32f4-bxcan
> - Rename master property to st,can-master.
> - Remove the status property from the example.
> - Put the node child properties as required.
>
> .../bindings/net/can/st,stm32-bxcan.yaml | 142 ++++++++++++++++++
> 1 file changed, 142 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml
> new file mode 100644
> index 000000000000..3278c724e6f5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml
> @@ -0,0 +1,142 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: STMicroelectronics bxCAN controller
> +
> +description: STMicroelectronics BxCAN controller for CAN bus
> +
> +maintainers:
> + - Dario Binacchi <dario.binacchi@...rulasolutions.com>
> +
> +allOf:
> + - $ref: can-controller.yaml#
> +
> +properties:
> + compatible:
> + description:
> + It manages the access to the 512-bytes SRAM memory shared by the
> + two bxCAN cells (CAN1 master and CAN2 slave) in dual CAN peripheral
> + configuration.
> + enum:
> + - st,stm32f4-bxcan-core
> +
> + reg:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + clocks:
> + description:
> + Input clock for registers access
> + maxItems: 1
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> +patternProperties:
> + "^can@[0-9]+$":
> + type: object
> + description:
> + A CAN block node contains two subnodes, representing each one a CAN
> + instance available on the machine.
> +
> + properties:
> + compatible:
> + enum:
> + - st,stm32f4-bxcan
> +
> + st,can-master:
> + description:
> + Master and slave mode of the bxCAN peripheral is only relevant
> + if the chip has two CAN peripherals. In that case they share
> + some of the required logic, and that means you cannot use the
> + slave CAN without the master CAN.
> + type: boolean
> +
> + reg:
> + description: |
> + Offset of CAN instance in CAN block. Valid values are:
> + - 0x0: CAN1
> + - 0x400: CAN2
> + maxItems: 1
> +
> + interrupts:
> + items:
> + - description: transmit interrupt
> + - description: FIFO 0 receive interrupt
> + - description: FIFO 1 receive interrupt
> + - description: status change error interrupt
> +
> + interrupt-names:
> + items:
> + - const: tx
> + - const: rx0
> + - const: rx1
> + - const: sce
> +
> + resets:
> + maxItems: 1
> +
> + clocks:
> + description:
> + Input clock for registers access
> + maxItems: 1
> +
> + additionalProperties: false
> +
> + required:
> + - compatible
> + - reg
> + - interrupts
> + - resets
> + - clocks
> +
> +required:
> + - compatible
> + - reg
> + - resets
> + - clocks
> + - '#address-cells'
> + - '#size-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/stm32fx-clock.h>
> + #include <dt-bindings/mfd/stm32f4-rcc.h>
> +
> + can: can@...06400 {
> + compatible = "st,stm32f4-bxcan-core";
> + reg = <0x40006400 0x800>;
> + resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
> + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
> + #address-cells = <1>;
> + #size-cells = <0>;
Again, the addressing is not correct here if 0 and 0x400 are memory
mapped register offsets.
Rob
> +
> + can1: can@0 {
> + compatible = "st,stm32f4-bxcan";
> + reg = <0x0>;
> + interrupts = <19>, <20>, <21>, <22>;
> + interrupt-names = "tx", "rx0", "rx1", "sce";
> + resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
> + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
> + st,can-master;
> + };
> +
> + can2: can@400 {
> + compatible = "st,stm32f4-bxcan";
> + reg = <0x400>;
> + interrupts = <63>, <64>, <65>, <66>;
> + interrupt-names = "tx", "rx0", "rx1", "sce";
> + resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
> + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
> + };
> + };
> --
> 2.32.0
>
>
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