linux-kernel - Re: [PATCH 08/15] cxl/acpi: Check RCH's CXL DVSEC capabilities

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 31 Aug 2022 11:52:24 +0100
From:   Jonathan Cameron <Jonathan.Cameron@...wei.com>
To:     Robert Richter <rrichter@....com>
CC:     Alison Schofield <alison.schofield@...el.com>,
        Vishal Verma <vishal.l.verma@...el.com>,
        Ira Weiny <ira.weiny@...el.com>,
        Ben Widawsky <bwidawsk@...nel.org>,
        Dan Williams <dan.j.williams@...el.com>,
        <linux-cxl@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        Len Brown <lenb@...nel.org>
Subject: Re: [PATCH 08/15] cxl/acpi: Check RCH's CXL DVSEC capabilities

On Wed, 31 Aug 2022 10:15:56 +0200
Robert Richter <rrichter@....com> wrote:

> An RCH has an RCiEP connected to it with CXL DVSEC capabilities
> present and the CXL PCIe DVSEC included. Check this.
> 
> Signed-off-by: Robert Richter <rrichter@....com>
One comment inline. This looks good to me.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>

> ---
>  drivers/cxl/acpi.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> index ffdf439adb87..f9cdf23a91a8 100644
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
> @@ -322,6 +322,8 @@ struct pci_host_bridge *cxl_find_next_rch(struct pci_host_bridge *host)
>  {
>  	struct pci_bus *bus = host ? host->bus : NULL;
>  	struct acpi_device *adev;
> +	struct pci_dev *pdev;
> +	bool is_restricted_host;
>  
>  	while ((bus = pci_find_next_bus(bus)) != NULL) {
>  		host = bus ? to_pci_host_bridge(bus->bridge) : NULL;
> @@ -343,6 +345,20 @@ struct pci_host_bridge *cxl_find_next_rch(struct pci_host_bridge *host)
>  		dev_dbg(&host->dev, "PCI ACPI host found: %s\n",
>  			acpi_dev_name(adev));
>  
> +		/* Check CXL DVSEC of dev 0 func 0 */

So assumption here is that the hostbridge has a one or more RCiEPs.
The spec (r3.0 9.11.4) allows for the EP to appear behind a root port
- that case always felt odd to me, so I'm fine with not supporting it until
we see a user.

> +		pdev = pci_get_slot(bus, PCI_DEVFN(0, 0));
> +		is_restricted_host = pdev
> +			&& (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
> +			&& pci_find_dvsec_capability(pdev,
> +						PCI_DVSEC_VENDOR_ID_CXL,
> +						CXL_DVSEC_PCIE_DEVICE);
> +		pci_dev_put(pdev);
> +
> +		if (!is_restricted_host)
> +			continue;
> +
> +		dev_dbg(&host->dev, "CXL restricted host found\n");
> +
>  		return host;
>  	}
>  
> @@ -354,6 +370,7 @@ static int __init cxl_restricted_host_probe(struct platform_device *pdev)
>  	struct pci_host_bridge *host = NULL;
>  
>  	while ((host = cxl_find_next_rch(host)) != NULL) {
> +		dev_info(&host->dev, "host supports CXL\n");
>  	}
>  
>  	return 0;