linux-kernel - Re: [PATCH 07/14] arm64: dts: qcom: sm6115: Add sdhci nodes and related pinctrl

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Message-ID: <339df7b9-bc7d-039d-99d8-ecdd480419d8@linaro.org>
Date:   Thu, 1 Sep 2022 19:08:20 +0300
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Iskren Chernev <iskren.chernev@...il.com>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Rob Herring <robh+dt@...nel.org>
Cc:     phone-devel@...r.kernel.org, ~postmarketos/upstreaming@...ts.sr.ht,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        Andy Gross <agross@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...ainline.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 07/14] arm64: dts: qcom: sm6115: Add sdhci nodes and
 related pinctrl

On 01/09/2022 10:24, Iskren Chernev wrote:
> Add support for the two sdhci's present on the SM6115 and the related
> pinctrl.
> 


>  
>  		gcc: clock-controller@...0000 {
> @@ -449,6 +553,73 @@ rpm_msg_ram: memory@...0000 {
>  			reg = <0x45f0000 0x7000>;
>  		};
>  
> +		sdhc_1: sdhci@...4000 {
> +			compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
> +			reg = <0x4744000 0x1000>, <0x4745000 0x1000>, <0x4748000 0x8000>;
> +			reg-names = "hc", "cqhci", "ice";
> +
> +			interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "hc_irq", "pwr_irq";
> +
> +			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> +				 <&gcc GCC_SDCC1_APPS_CLK>,
> +				 <&xo_board>,
> +				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> +			clock-names = "iface", "core", "xo", "ice_core_clk";

Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).

> +

Best regards,
Krzysztof