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Date: Mon, 5 Sep 2022 15:30:08 +0200 From: Linus Walleij <linus.walleij@...aro.org> To: Andy Shevchenko <andriy.shevchenko@...ux.intel.com> Cc: Patrick Rudolph <patrick.rudolph@...ements.com>, "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org> Subject: Re: [PATCH v1 03/17] pinctrl: cy8c95x0: Allow most of the registers to be cached On Mon, Sep 5, 2022 at 2:57 PM Andy Shevchenko <andriy.shevchenko@...ux.intel.com> wrote: > On Fri, Sep 02, 2022 at 09:42:00PM +0300, Andy Shevchenko wrote: > > On Fri, Sep 2, 2022 at 9:36 PM Andy Shevchenko > > <andriy.shevchenko@...ux.intel.com> wrote: > > > > > > It's unclear why many of static registers were marked as volatile. > > > > the static (yeah, forgot it) > > > > > They are pretty much bidirectional and static in a sense that > > > written value is kept there until a new write or chip reset. > > > Drop those registers from the list to allow them to be cached. > > > > This patch is not correct due to indexing access. It's sneaked since I > > forgot I added it into my main repo. The proper approach should be to > > create virtual registers and decode them before use. This allows to > > cache all ports and as a benefit to debug print all port actual > > statuses. > > To be clear: With this one removed from the bunch the rest can be applied w.o. > any change. I'll give Patrick a day or two to test/review and then I'll just apply them all except this one, they are all pretty self-evident except ACPI things which have obviously been tested on hardware so from my point of view it's good to merge. Yours, Linus Walleij
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