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Message-ID: <DM6PR12MB30829DDDC62B36B17F87B204E8419@DM6PR12MB3082.namprd12.prod.outlook.com>
Date: Wed, 7 Sep 2022 03:17:34 +0000
From: "Gupta, Nipun" <Nipun.Gupta@....com>
To: Saravana Kannan <saravanak@...gle.com>
CC: "robh+dt@...nel.org" <robh+dt@...nel.org>,
"krzysztof.kozlowski+dt@...aro.org"
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Subject: RE: [RFC PATCH v3 3/7] iommu/arm-smmu-v3: support ops registration
for CDX bus
[AMD Official Use Only - General]
> -----Original Message-----
> From: Saravana Kannan <saravanak@...gle.com>
> Sent: Wednesday, September 7, 2022 5:41 AM
> To: Gupta, Nipun <Nipun.Gupta@....com>
> Cc: robh+dt@...nel.org; krzysztof.kozlowski+dt@...aro.org;
> gregkh@...uxfoundation.org; rafael@...nel.org; eric.auger@...hat.com;
> alex.williamson@...hat.com; cohuck@...hat.com; Gupta, Puneet (DCG-ENG)
> <puneet.gupta@....com>; song.bao.hua@...ilicon.com;
> mchehab+huawei@...nel.org; maz@...nel.org; f.fainelli@...il.com;
> jeffrey.l.hugo@...il.com; Michael.Srba@...nam.cz; mani@...nel.org;
> yishaih@...dia.com; jgg@...pe.ca; jgg@...dia.com; robin.murphy@....com;
> will@...nel.org; joro@...tes.org; masahiroy@...nel.org;
> ndesaulniers@...gle.com; linux-arm-kernel@...ts.infradead.org; linux-
> kbuild@...r.kernel.org; linux-kernel@...r.kernel.org;
> devicetree@...r.kernel.org; kvm@...r.kernel.org; okaya@...nel.org; Anand,
> Harpreet <harpreet.anand@....com>; Agarwal, Nikhil
> <nikhil.agarwal@....com>; Simek, Michal <michal.simek@....com>;
> Radovanovic, Aleksandar <aleksandar.radovanovic@....com>; git (AMD-Xilinx)
> <git@....com>
> Subject: Re: [RFC PATCH v3 3/7] iommu/arm-smmu-v3: support ops registration
> for CDX bus
>
> [CAUTION: External Email]
>
> On Tue, Sep 6, 2022 at 6:48 AM Nipun Gupta <nipun.gupta@....com> wrote:
> >
> > With new CDX bus supported for AMD FPGA devices on ARM
> > platform, the bus requires registration for the SMMU v3
> > driver.
> >
> > Signed-off-by: Nipun Gupta <nipun.gupta@....com>
> > ---
> > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 ++++++++++++++--
> > 1 file changed, 14 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> > index d32b02336411..8ec9f2baf12d 100644
> > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> > @@ -29,6 +29,7 @@
> > #include <linux/platform_device.h>
> >
> > #include <linux/amba/bus.h>
> > +#include <linux/cdx/cdx_bus.h>
> >
> > #include "arm-smmu-v3.h"
> > #include "../../iommu-sva-lib.h"
> > @@ -3690,16 +3691,27 @@ static int arm_smmu_set_bus_ops(struct
> iommu_ops *ops)
> > if (err)
> > goto err_reset_pci_ops;
> > }
> > +#endif
> > +#ifdef CONFIG_CDX_BUS
> > + if (cdx_bus_type.iommu_ops != ops) {
> > + err = bus_set_iommu(&cdx_bus_type, ops);
> > + if (err)
> > + goto err_reset_amba_ops;
> > + }
>
> I'm not an expert on IOMMUs, so apologies if the question is stupid.
>
> Why does the CDX bus need special treatment here (like PCI) when there
> are so many other busses (eg: I2C, SPI, etc) that don't need any
> changes here?
AFAIU, the devices on I2C/SPI does not use SMMU. Apart from PCI/AMBA,
FSL-MC is another similar bus (on SMMUv2) which uses SMMU ops.
The devices here are behind SMMU. Robin can kindly correct or add
more here from SMMU perspective.
Thanks,
Nipun
>
> -Saravana
>
> > #endif
> > if (platform_bus_type.iommu_ops != ops) {
> > err = bus_set_iommu(&platform_bus_type, ops);
> > if (err)
> > - goto err_reset_amba_ops;
> > + goto err_reset_cdx_ops;
> > }
> >
> > return 0;
> >
> > -err_reset_amba_ops:
> > +err_reset_cdx_ops:
> > +#ifdef CONFIG_CDX_BUS
> > + bus_set_iommu(&cdx_bus_type, NULL);
> > +#endif
> > +err_reset_amba_ops: __maybe_unused;
> > #ifdef CONFIG_ARM_AMBA
> > bus_set_iommu(&amba_bustype, NULL);
> > #endif
> > --
> > 2.25.1
> >
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