linux-kernel - Re: [PATCH v3] spi: Add capability to perform some transfer with chipselect off

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Message-ID: <YxiEEP3krNUiUvlg@sirena.org.uk>
Date:   Wed, 7 Sep 2022 12:44:16 +0100
From:   Mark Brown <broonie@...nel.org>
To:     Christophe Leroy <christophe.leroy@...roup.eu>
Cc:     linux-kernel@...r.kernel.org, linux-spi@...r.kernel.org
Subject: Re: [PATCH v3] spi: Add capability to perform some transfer with
 chipselect off

On Thu, Aug 18, 2022 at 03:57:49PM +0200, Christophe Leroy wrote:
> Some components require a few clock cycles with chipselect off before
> or/and after the data transfer done with CS on.
> 
> Typically IDT 801034 QUAD PCM CODEC datasheet states "Note *: CCLK
> should have one cycle before CS goes low, and two cycles after
> CS goes high".

This doesn't apply against current code, please check and resend.

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