linux-kernel - Re: [PATCH v3] spi: Add capability to perform some transfer with chipselect off

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <b8f85b72-5313-affb-3402-70e2102d1383@csgroup.eu>
Date:   Wed, 7 Sep 2022 14:15:40 +0000
From:   Christophe Leroy <christophe.leroy@...roup.eu>
To:     Mark Brown <broonie@...nel.org>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>
Subject: Re: [PATCH v3] spi: Add capability to perform some transfer with
 chipselect off



Le 07/09/2022 à 13:44, Mark Brown a écrit :
> On Thu, Aug 18, 2022 at 03:57:49PM +0200, Christophe Leroy wrote:
>> Some components require a few clock cycles with chipselect off before
>> or/and after the data transfer done with CS on.
>>
>> Typically IDT 801034 QUAD PCM CODEC datasheet states "Note *: CCLK
>> should have one cycle before CS goes low, and two cycles after
>> CS goes high".
> 
> This doesn't apply against current code, please check and resend.

Looks like my patch was from before the percpu statistics.

I just sent a rebased patch.

Christophe