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Message-ID: <e2a8edee-3bf3-2ab9-48c3-9f6f3c04f3b9@microchip.com>
Date: Thu, 8 Sep 2022 06:46:46 +0000
From: <Claudiu.Beznea@...rochip.com>
To: <Conor.Dooley@...rochip.com>, <mturquette@...libre.com>,
<sboyd@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <palmer@...belt.com>,
<Daire.McNamara@...rochip.com>
CC: <paul.walmsley@...ive.com>, <aou@...s.berkeley.edu>,
<linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>
Subject: Re: [PATCH v4 09/13] clk: microchip: mpfs: simplify control reg
access
On 30.08.2022 15:52, Conor Dooley wrote:
> The control reg addresses are known when the clocks are registered, so
> we can, instead of assigning a base pointer to the structs, assign the
> control reg addresses directly. Accordingly, remove the interim
> variables used during reads/writes to those registers.
>
> Reviewed-by: Daire McNamara <daire.mcnamara@...rochip.com>
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
> ---
> drivers/clk/microchip/clk-mpfs.c | 42 +++++++++++++-------------------
> 1 file changed, 17 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c
> index 845658751690..60e1e82912fe 100644
> --- a/drivers/clk/microchip/clk-mpfs.c
> +++ b/drivers/clk/microchip/clk-mpfs.c
> @@ -52,6 +52,7 @@ struct mpfs_msspll_hw_clock {
> #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
>
> struct mpfs_cfg_clock {
> + void __iomem *reg;
> const struct clk_div_table *table;
> u8 shift;
> u8 width;
> @@ -60,7 +61,6 @@ struct mpfs_cfg_clock {
>
> struct mpfs_cfg_hw_clock {
> struct mpfs_cfg_clock cfg;
> - void __iomem *sys_base;
> struct clk_hw hw;
> struct clk_init_data init;
> unsigned int id;
> @@ -70,12 +70,12 @@ struct mpfs_cfg_hw_clock {
> #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw)
>
> struct mpfs_periph_clock {
> + void __iomem *reg;
> u8 shift;
> };
>
> struct mpfs_periph_hw_clock {
> struct mpfs_periph_clock periph;
> - void __iomem *sys_base;
> struct clk_hw hw;
> unsigned int id;
> };
> @@ -214,14 +214,13 @@ static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_cl
> static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws,
> unsigned int num_clks, struct mpfs_clock_data *data)
> {
> - void __iomem *base = data->msspll_base;
> unsigned int i;
> int ret;
>
> for (i = 0; i < num_clks; i++) {
> struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i];
>
> - ret = mpfs_clk_register_msspll(dev, msspll_hw, base);
> + ret = mpfs_clk_register_msspll(dev, msspll_hw, data->msspll_base);
> if (ret)
> return dev_err_probe(dev, ret, "failed to register msspll id: %d\n",
> CLK_MSSPLL);
> @@ -240,10 +239,9 @@ static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long p
> {
> struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
> struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
> - void __iomem *base_addr = cfg_hw->sys_base;
> u32 val;
>
> - val = readl_relaxed(base_addr + cfg_hw->reg_offset) >> cfg->shift;
> + val = readl_relaxed(cfg->reg) >> cfg->shift;
> val &= clk_div_mask(cfg->width);
>
> return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width);
> @@ -261,7 +259,6 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned
> {
> struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
> struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
> - void __iomem *base_addr = cfg_hw->sys_base;
> unsigned long flags;
> u32 val;
> int divider_setting;
> @@ -272,10 +269,10 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned
> return divider_setting;
>
> spin_lock_irqsave(&mpfs_clk_lock, flags);
> - val = readl_relaxed(base_addr + cfg_hw->reg_offset);
> + val = readl_relaxed(cfg->reg);
> val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);
> val |= divider_setting << cfg->shift;
> - writel_relaxed(val, base_addr + cfg_hw->reg_offset);
> + writel_relaxed(val, cfg->reg);
>
> spin_unlock_irqrestore(&mpfs_clk_lock, flags);
>
> @@ -318,9 +315,9 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
> };
>
> static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw,
> - void __iomem *sys_base)
> + void __iomem *base)
> {
> - cfg_hw->sys_base = sys_base;
> + cfg_hw->cfg.reg = base + cfg_hw->reg_offset;
>
> return devm_clk_hw_register(dev, &cfg_hw->hw);
> }
> @@ -328,14 +325,13 @@ static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *c
> static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws,
> unsigned int num_clks, struct mpfs_clock_data *data)
> {
> - void __iomem *sys_base = data->base;
> unsigned int i, id;
> int ret;
>
> for (i = 0; i < num_clks; i++) {
> struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
>
> - ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base);
> + ret = mpfs_clk_register_cfg(dev, cfg_hw, data->base);
> if (ret)
> return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
> cfg_hw->id);
> @@ -355,15 +351,14 @@ static int mpfs_periph_clk_enable(struct clk_hw *hw)
> {
> struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
> struct mpfs_periph_clock *periph = &periph_hw->periph;
> - void __iomem *base_addr = periph_hw->sys_base;
> u32 reg, val;
> unsigned long flags;
>
> spin_lock_irqsave(&mpfs_clk_lock, flags);
>
> - reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
> + reg = readl_relaxed(periph->reg);
> val = reg | (1u << periph->shift);
> - writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR);
> + writel_relaxed(val, periph->reg);
>
> spin_unlock_irqrestore(&mpfs_clk_lock, flags);
>
> @@ -374,15 +369,14 @@ static void mpfs_periph_clk_disable(struct clk_hw *hw)
> {
> struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
> struct mpfs_periph_clock *periph = &periph_hw->periph;
> - void __iomem *base_addr = periph_hw->sys_base;
> u32 reg, val;
> unsigned long flags;
>
> spin_lock_irqsave(&mpfs_clk_lock, flags);
>
> - reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
> + reg = readl_relaxed(periph->reg);
> val = reg & ~(1u << periph->shift);
> - writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR);
> + writel_relaxed(val, periph->reg);
>
> spin_unlock_irqrestore(&mpfs_clk_lock, flags);
> }
> @@ -391,10 +385,9 @@ static int mpfs_periph_clk_is_enabled(struct clk_hw *hw)
> {
> struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
> struct mpfs_periph_clock *periph = &periph_hw->periph;
> - void __iomem *base_addr = periph_hw->sys_base;
> u32 reg;
>
> - reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
> + reg = readl_relaxed(periph->reg);
> if (reg & (1u << periph->shift))
> return 1;
>
> @@ -462,9 +455,9 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
> };
>
> static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw,
> - void __iomem *sys_base)
> + void __iomem *base)
> {
> - periph_hw->sys_base = sys_base;
> + periph_hw->periph.reg = base + REG_SUBBLK_CLOCK_CR;
>
> return devm_clk_hw_register(dev, &periph_hw->hw);
> }
> @@ -472,14 +465,13 @@ static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_cl
> static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws,
> int num_clks, struct mpfs_clock_data *data)
> {
> - void __iomem *sys_base = data->base;
> unsigned int i, id;
> int ret;
>
> for (i = 0; i < num_clks; i++) {
> struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
>
> - ret = mpfs_clk_register_periph(dev, periph_hw, sys_base);
> + ret = mpfs_clk_register_periph(dev, periph_hw, data->base);
> if (ret)
> return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
> periph_hw->id);
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