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Message-ID: <919bfaae-0a1d-de88-8211-f9fa476e6ebf@arm.com>
Date: Thu, 8 Sep 2022 12:49:05 +0100
From: Robin Murphy <robin.murphy@....com>
To: "Radovanovic, Aleksandar" <aleksandar.radovanovic@....com>,
Marc Zyngier <maz@...nel.org>
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Subject: Re: [RFC PATCH v3 4/7] bus/cdx: add cdx-MSI domain with gic-its
domain as parent
On 2022-09-08 10:51, Radovanovic, Aleksandar wrote:
> [AMD Official Use Only - General]
>
>
>
>> -----Original Message-----
>> From: Marc Zyngier <maz@...nel.org>
>> Sent: 08 September 2022 09:08
>> To: Radovanovic, Aleksandar <aleksandar.radovanovic@....com>
>> Cc: Jason Gunthorpe <jgg@...dia.com>; Gupta, Nipun
>> <Nipun.Gupta@....com>; robh+dt@...nel.org;
>> krzysztof.kozlowski+dt@...aro.org; gregkh@...uxfoundation.org;
>> rafael@...nel.org; eric.auger@...hat.com; alex.williamson@...hat.com;
>> cohuck@...hat.com; Gupta, Puneet (DCG-ENG)
>> <puneet.gupta@....com>; song.bao.hua@...ilicon.com;
>> mchehab+huawei@...nel.org; f.fainelli@...il.com;
>> jeffrey.l.hugo@...il.com; saravanak@...gle.com;
>> Michael.Srba@...nam.cz; mani@...nel.org; yishaih@...dia.com;
>> robin.murphy@....com; will@...nel.org; joro@...tes.org;
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>> okaya@...nel.org; Anand, Harpreet <harpreet.anand@....com>; Agarwal,
>> Nikhil <nikhil.agarwal@....com>; Simek, Michal <michal.simek@....com>;
>> git (AMD-Xilinx) <git@....com>
>> Subject: Re: [RFC PATCH v3 4/7] bus/cdx: add cdx-MSI domain with gic-its
>> domain as parent
>>
>> [CAUTION: External Email]
>>
>> OK, so you definitely need a mapping, but it cannot be a translation, and it
>> needs to be in all the possible address spaces. OMG.
>
> Could you elaborate why it needs to be in all the possible address spaces? I'm in no way familiar with kernel IOVA allocation, so not sure I understand this requirement. Note that each CDX device will have its own unique StreamID (in general case, equal to DeviceID sent to the GIC), so, from a SMMU perspective, the mapping can be specific to that device. As long as that IOVA is not allocated to any DMA region for _that_ device, things should be OK? But, I appreciate it might not be that simple from a kernel perspective.
That's the point - any device could could have its own mapping,
therefore that hole has to be punched in *every* mapping that any of
those devices could use, so that MSI writes don't unexpectedly fault, or
corrupt memory if that address is free to be used to map a DMA buffer.
At least the HiSilicon PCI quirk is functionally similar (for slightly
different underlying reasons) so there's already precedent and an
example that you can follow to a reasonable degree.
Robin.
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