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Message-ID: <CA+V-a8uttuVd5_UXvNjXU6yG-GpmxG-BuEAm9pWxx13PjZ-h5w@mail.gmail.com>
Date: Thu, 8 Sep 2022 12:50:58 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: guoren@...ux.alibaba.com,
"Conor.Dooley@...rochip.com" <Conor.Dooley@...rochip.com>
Cc: "atishp@...shpatra.org" <atishp@...shpatra.org>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
"paul.walmsley@...ive.com" <paul.walmsley@...ive.com>,
Biju Das <biju.das.jz@...renesas.com>,
"palmer@...belt.com" <palmer@...belt.com>,
"aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
"atishp@...osinc.com" <atishp@...osinc.com>,
"apatel@...tanamicro.com" <apatel@...tanamicro.com>,
"geert+renesas@...der.be" <geert+renesas@...der.be>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
"linux-renesas-soc@...r.kernel.org"
<linux-renesas-soc@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [RFC PATCH 1/2] riscv: vendors: andes: Add support to configure
the PMA regions
Hi Guo,
> > -----Original Message-----
> > From: Conor.Dooley@...rochip.com <Conor.Dooley@...rochip.com>
> > Sent: 08 September 2022 00:38
> > To: atishp@...shpatra.org
> > Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>;
> > paul.walmsley@...ive.com; palmer@...belt.com; aou@...s.berkeley.edu;
> > atishp@...osinc.com; apatel@...tanamicro.com; geert+renesas@...der.be;
> > linux-riscv@...ts.infradead.org; linux-renesas-soc@...r.kernel.org;
> > linux-kernel@...r.kernel.org; prabhakar.csengg@...il.com; Biju Das
> > <biju.das.jz@...renesas.com>
> > Subject: Re: [RFC PATCH 1/2] riscv: vendors: andes: Add support to
> > configure the PMA regions
> >
> > On 07/09/2022 22:52, Atish Patra wrote:
> > > EXTERNAL EMAIL: Do not click links or open attachments unless you know
> > > the content is safe
> > >
> > >
> > > On Tue, Sep 6, 2022 at 3:40 AM <Conor.Dooley@...rochip.com
> > > <mailto:Conor.Dooley@...rochip.com>> wrote:
> > >
> > > On 06/09/2022 11:21, Lad Prabhakar wrote:
> > >
> > >> diff --git a/arch/riscv/include/asm/sbi.h
> > >> b/arch/riscv/include/asm/sbi.h index 2a0ef738695e..10a7c855d125
> > >> 100644 --- a/arch/riscv/include/asm/sbi.h +++
> > >> b/arch/riscv/include/asm/sbi.h @@ -37,6 +37,7 @@ enum sbi_ext_id {
> > >>
> > >> /* Vendor extensions must lie within this range */
> > >> SBI_EXT_VENDOR_START = 0x09000000, + SBI_EXT_ANDES =
> > >> 0x0900031E, SBI_EXT_VENDOR_END = 0x09FFFFFF, };
> > >
I am interested to know what is the status of your patch series [0].
[0] https://lore.kernel.org/lkml/20210606143848.GA5983@lst.de/T/#m7f4c4cdfb92d6c8672bbfabebda729ce4700e177
Cheers,
Prabhakar
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