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Message-ID: <202209081929.lspliJeb-lkp@intel.com>
Date: Thu, 8 Sep 2022 19:51:06 +0800
From: kernel test robot <lkp@...el.com>
To: Mark Rutland <mark.rutland@....com>
Cc: kbuild-all@...ts.01.org, linux-kernel@...r.kernel.org
Subject: [mark:arm64/insn/rework-redo 14/14]
arch/arm64/lib/test_insn.c:43:23: error: implicit declaration of function
'aarch64_insn_decode_register'; did you mean
'aarch64_insn_decode_register_rs'?
Hi Mark,
FYI, the error/warning was bisected to this commit, please ignore it if it's irrelevant.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git arm64/insn/rework-redo
head: 1acba155a82179ec37833745242a4998d2b2da0e
commit: 1acba155a82179ec37833745242a4998d2b2da0e [14/14] arm64: insn: rework register manipulation
config: arm64-randconfig-c032-20220908
compiler: aarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git/commit/?id=1acba155a82179ec37833745242a4998d2b2da0e
git remote add mark https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git
git fetch --no-tags mark arm64/insn/rework-redo
git checkout 1acba155a82179ec37833745242a4998d2b2da0e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@...el.com>
All errors (new ones prefixed by >>):
arch/arm64/lib/test_insn.c:35:6: warning: no previous prototype for 'test_insn_adr' [-Wmissing-prototypes]
35 | void test_insn_adr(struct kunit *test)
| ^~~~~~~~~~~~~
arch/arm64/lib/test_insn.c: In function 'test_insn_adr':
>> arch/arm64/lib/test_insn.c:43:23: error: implicit declaration of function 'aarch64_insn_decode_register'; did you mean 'aarch64_insn_decode_register_rs'? [-Werror=implicit-function-declaration]
43 | u32 obj_reg = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, obj_insn); \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:53:9: note: in expansion of macro 'TEST_ADR_CASE'
53 | TEST_ADR_CASE(test, "x0", AARCH64_INSN_REG_0, 0);
| ^~~~~~~~~~~~~
>> arch/arm64/lib/test_insn.c:43:52: error: 'AARCH64_INSN_REGTYPE_RD' undeclared (first use in this function); did you mean 'AARCH64_INSN_ADR_TYPE_ADR'?
43 | u32 obj_reg = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, obj_insn); \
| ^~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:53:9: note: in expansion of macro 'TEST_ADR_CASE'
53 | TEST_ADR_CASE(test, "x0", AARCH64_INSN_REG_0, 0);
| ^~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:43:52: note: each undeclared identifier is reported only once for each function it appears in
43 | u32 obj_reg = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, obj_insn); \
| ^~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:53:9: note: in expansion of macro 'TEST_ADR_CASE'
53 | TEST_ADR_CASE(test, "x0", AARCH64_INSN_REG_0, 0);
| ^~~~~~~~~~~~~
arch/arm64/lib/test_insn.c: At top level:
arch/arm64/lib/test_insn.c:77:6: warning: no previous prototype for 'test_insn_adrp' [-Wmissing-prototypes]
77 | void test_insn_adrp(struct kunit *test)
| ^~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c: In function 'test_insn_adrp':
arch/arm64/lib/test_insn.c:85:52: error: 'AARCH64_INSN_REGTYPE_RD' undeclared (first use in this function); did you mean 'AARCH64_INSN_ADR_TYPE_ADR'?
85 | u32 obj_reg = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, obj_insn); \
| ^~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:95:9: note: in expansion of macro 'TEST_ADRP_CASE'
95 | TEST_ADRP_CASE(test, "x0", AARCH64_INSN_REG_0, 0);
| ^~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c: At top level:
arch/arm64/lib/test_insn.c:123:6: warning: no previous prototype for 'test_insn_ldxr' [-Wmissing-prototypes]
123 | void test_insn_ldxr(struct kunit *test)
| ^~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c: In function 'test_insn_ldxr':
>> arch/arm64/lib/test_insn.c:135:51: error: 'AARCH64_INSN_REGTYPE_RT' undeclared (first use in this function); did you mean 'AARCH64_INSN_PRFM_TYPE_PST'?
135 | u32 obj_rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, obj_insn); \
| ^~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:147:9: note: in expansion of macro 'TEST_LDXR_CASE'
147 | TEST_LDXR_CASE(test, "ldaxr",
| ^~~~~~~~~~~~~~
>> arch/arm64/lib/test_insn.c:136:51: error: 'AARCH64_INSN_REGTYPE_RN' undeclared (first use in this function); did you mean 'AARCH64_INSN_REG_SP'?
136 | u32 obj_rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, obj_insn); \
| ^~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:147:9: note: in expansion of macro 'TEST_LDXR_CASE'
147 | TEST_LDXR_CASE(test, "ldaxr",
| ^~~~~~~~~~~~~~
>> arch/arm64/lib/test_insn.c:137:51: error: 'AARCH64_INSN_REGTYPE_RS' undeclared (first use in this function); did you mean 'AARCH64_INSN_PRFM_TYPE_PST'?
137 | u32 obj_rs = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RS, obj_insn); \
| ^~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:147:9: note: in expansion of macro 'TEST_LDXR_CASE'
147 | TEST_LDXR_CASE(test, "ldaxr",
| ^~~~~~~~~~~~~~
>> arch/arm64/lib/test_insn.c:138:52: error: 'AARCH64_INSN_REGTYPE_RT2' undeclared (first use in this function); did you mean 'AARCH64_INSN_REG_22'?
138 | u32 obj_rt2 = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT2, obj_insn); \
| ^~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:147:9: note: in expansion of macro 'TEST_LDXR_CASE'
147 | TEST_LDXR_CASE(test, "ldaxr",
| ^~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c: At top level:
arch/arm64/lib/test_insn.c:195:6: warning: no previous prototype for 'test_insn_stxr' [-Wmissing-prototypes]
195 | void test_insn_stxr(struct kunit *test)
| ^~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c: In function 'test_insn_stxr':
arch/arm64/lib/test_insn.c:206:51: error: 'AARCH64_INSN_REGTYPE_RT' undeclared (first use in this function); did you mean 'AARCH64_INSN_PRFM_TYPE_PST'?
206 | u32 obj_rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, obj_insn); \
| ^~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:218:9: note: in expansion of macro 'TEST_STXR_CASE'
218 | TEST_STXR_CASE(test, "stlxr",
| ^~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:207:51: error: 'AARCH64_INSN_REGTYPE_RN' undeclared (first use in this function); did you mean 'AARCH64_INSN_REG_SP'?
207 | u32 obj_rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, obj_insn); \
| ^~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:218:9: note: in expansion of macro 'TEST_STXR_CASE'
218 | TEST_STXR_CASE(test, "stlxr",
| ^~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:208:51: error: 'AARCH64_INSN_REGTYPE_RS' undeclared (first use in this function); did you mean 'AARCH64_INSN_PRFM_TYPE_PST'?
208 | u32 obj_rs = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RS, obj_insn); \
| ^~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:218:9: note: in expansion of macro 'TEST_STXR_CASE'
218 | TEST_STXR_CASE(test, "stlxr",
| ^~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:209:52: error: 'AARCH64_INSN_REGTYPE_RT2' undeclared (first use in this function); did you mean 'AARCH64_INSN_REG_22'?
209 | u32 obj_rt2 = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT2, obj_insn); \
| ^~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/lib/test_insn.c:218:9: note: in expansion of macro 'TEST_STXR_CASE'
218 | TEST_STXR_CASE(test, "stlxr",
| ^~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +43 arch/arm64/lib/test_insn.c
1a7152b762288c Mark Rutland 2022-09-05 31
1a7152b762288c Mark Rutland 2022-09-05 32 #define INSN_AS_U32(insn, inputs...) \
1a7152b762288c Mark Rutland 2022-09-05 33 __INSN_AS_U32(__UNIQUE_ID(opcode), insn, inputs)
1a7152b762288c Mark Rutland 2022-09-05 34
1a7152b762288c Mark Rutland 2022-09-05 35 void test_insn_adr(struct kunit *test)
1a7152b762288c Mark Rutland 2022-09-05 36 {
1a7152b762288c Mark Rutland 2022-09-05 37 #define TEST_ADR_CASE(test, asm_reg, gen_reg, offset) \
1a7152b762288c Mark Rutland 2022-09-05 38 do { \
1a7152b762288c Mark Rutland 2022-09-05 39 long gen_offset = 0UL + offset; \
1a7152b762288c Mark Rutland 2022-09-05 40 u32 gen_insn = aarch64_insn_gen_adr(0, gen_offset, gen_reg, \
1a7152b762288c Mark Rutland 2022-09-05 41 AARCH64_INSN_ADR_TYPE_ADR); \
1a7152b762288c Mark Rutland 2022-09-05 42 u32 obj_insn = INSN_AS_U32("adr " asm_reg ", . + %0", "i" (gen_offset)); \
1a7152b762288c Mark Rutland 2022-09-05 @43 u32 obj_reg = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, obj_insn); \
1a7152b762288c Mark Rutland 2022-09-05 44 s64 obj_offset = aarch64_insn_adr_get_offset(obj_insn); \
e0bba9be249a4d Mark Rutland 2022-09-08 45 s64 imm_offset = aarch64_insn_decode_signed_adr_imm(obj_insn); \
1a7152b762288c Mark Rutland 2022-09-05 46 KUNIT_EXPECT_TRUE(test, aarch64_insn_is_adr(obj_insn)); \
1a7152b762288c Mark Rutland 2022-09-05 47 KUNIT_EXPECT_EQ(test, obj_reg, gen_reg); \
1a7152b762288c Mark Rutland 2022-09-05 48 KUNIT_EXPECT_EQ(test, obj_offset, gen_offset); \
e0bba9be249a4d Mark Rutland 2022-09-08 49 KUNIT_EXPECT_EQ(test, obj_offset, imm_offset); \
1a7152b762288c Mark Rutland 2022-09-05 50 KUNIT_EXPECT_EQ(test, obj_insn, gen_insn); \
1a7152b762288c Mark Rutland 2022-09-05 51 } while (0)
1a7152b762288c Mark Rutland 2022-09-05 52
1a7152b762288c Mark Rutland 2022-09-05 53 TEST_ADR_CASE(test, "x0", AARCH64_INSN_REG_0, 0);
1a7152b762288c Mark Rutland 2022-09-05 54 TEST_ADR_CASE(test, "x1", AARCH64_INSN_REG_1, 0);
1a7152b762288c Mark Rutland 2022-09-05 55 TEST_ADR_CASE(test, "x2", AARCH64_INSN_REG_2, 257);
1a7152b762288c Mark Rutland 2022-09-05 56 TEST_ADR_CASE(test, "x3", AARCH64_INSN_REG_3, -923);
1a7152b762288c Mark Rutland 2022-09-05 57 TEST_ADR_CASE(test, "x4", AARCH64_INSN_REG_4, SZ_512K);
1a7152b762288c Mark Rutland 2022-09-05 58 TEST_ADR_CASE(test, "x5", AARCH64_INSN_REG_5, -SZ_512K);
1a7152b762288c Mark Rutland 2022-09-05 59 TEST_ADR_CASE(test, "x6", AARCH64_INSN_REG_6, SZ_1M - 1);
1a7152b762288c Mark Rutland 2022-09-05 60 TEST_ADR_CASE(test, "x7", AARCH64_INSN_REG_7, -SZ_1M);
1a7152b762288c Mark Rutland 2022-09-05 61
1a7152b762288c Mark Rutland 2022-09-05 62 #undef TEST_ADR_CASE
1a7152b762288c Mark Rutland 2022-09-05 63
1a7152b762288c Mark Rutland 2022-09-05 64 /*
1a7152b762288c Mark Rutland 2022-09-05 65 * Out-of-range immediates
1a7152b762288c Mark Rutland 2022-09-05 66 */
1a7152b762288c Mark Rutland 2022-09-05 67 KUNIT_EXPECT_EQ(test, AARCH64_BREAK_FAULT,
1a7152b762288c Mark Rutland 2022-09-05 68 aarch64_insn_gen_adr(0, SZ_1M,
1a7152b762288c Mark Rutland 2022-09-05 69 AARCH64_INSN_REG_0,
1a7152b762288c Mark Rutland 2022-09-05 70 AARCH64_INSN_ADR_TYPE_ADR));
1a7152b762288c Mark Rutland 2022-09-05 71 KUNIT_EXPECT_EQ(test, AARCH64_BREAK_FAULT,
1a7152b762288c Mark Rutland 2022-09-05 72 aarch64_insn_gen_adr(0, -SZ_1M + -1,
1a7152b762288c Mark Rutland 2022-09-05 73 AARCH64_INSN_REG_0,
1a7152b762288c Mark Rutland 2022-09-05 74 AARCH64_INSN_ADR_TYPE_ADR));
1a7152b762288c Mark Rutland 2022-09-05 75 }
1a7152b762288c Mark Rutland 2022-09-05 76
1a7152b762288c Mark Rutland 2022-09-05 77 void test_insn_adrp(struct kunit *test)
1a7152b762288c Mark Rutland 2022-09-05 78 {
1a7152b762288c Mark Rutland 2022-09-05 79 #define TEST_ADRP_CASE(test, asm_reg, gen_reg, _gen_offset) \
1a7152b762288c Mark Rutland 2022-09-05 80 do { \
1a7152b762288c Mark Rutland 2022-09-05 81 long gen_offset = 0UL + _gen_offset; \
1a7152b762288c Mark Rutland 2022-09-05 82 u32 gen_insn = aarch64_insn_gen_adr(0, gen_offset, gen_reg, \
1a7152b762288c Mark Rutland 2022-09-05 83 AARCH64_INSN_ADR_TYPE_ADRP); \
1a7152b762288c Mark Rutland 2022-09-05 84 u32 obj_insn = INSN_AS_U32("adrp " asm_reg ", . + %0", "i" (gen_offset)); \
1a7152b762288c Mark Rutland 2022-09-05 85 u32 obj_reg = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, obj_insn); \
1a7152b762288c Mark Rutland 2022-09-05 86 s64 obj_offset = aarch64_insn_adrp_get_offset(obj_insn); \
e0bba9be249a4d Mark Rutland 2022-09-08 87 s64 imm_offset = aarch64_insn_decode_scaled_signed_adr_imm(obj_insn, 4096); \
1a7152b762288c Mark Rutland 2022-09-05 88 KUNIT_EXPECT_TRUE(test, aarch64_insn_is_adrp(obj_insn)); \
1a7152b762288c Mark Rutland 2022-09-05 89 KUNIT_EXPECT_EQ(test, obj_reg, gen_reg); \
1a7152b762288c Mark Rutland 2022-09-05 90 KUNIT_EXPECT_EQ(test, obj_offset, gen_offset); \
e0bba9be249a4d Mark Rutland 2022-09-08 91 KUNIT_EXPECT_EQ(test, obj_offset, imm_offset); \
1a7152b762288c Mark Rutland 2022-09-05 92 KUNIT_EXPECT_EQ(test, obj_insn, gen_insn); \
1a7152b762288c Mark Rutland 2022-09-05 93 } while (0)
1a7152b762288c Mark Rutland 2022-09-05 94
1a7152b762288c Mark Rutland 2022-09-05 95 TEST_ADRP_CASE(test, "x0", AARCH64_INSN_REG_0, 0);
1a7152b762288c Mark Rutland 2022-09-05 96 TEST_ADRP_CASE(test, "x1", AARCH64_INSN_REG_1, 0);
1a7152b762288c Mark Rutland 2022-09-05 97 TEST_ADRP_CASE(test, "x2", AARCH64_INSN_REG_2, SZ_4K);
1a7152b762288c Mark Rutland 2022-09-05 98 TEST_ADRP_CASE(test, "x3", AARCH64_INSN_REG_3, -SZ_4K);
1a7152b762288c Mark Rutland 2022-09-05 99 TEST_ADRP_CASE(test, "x4", AARCH64_INSN_REG_4, SZ_1G);
1a7152b762288c Mark Rutland 2022-09-05 100 TEST_ADRP_CASE(test, "x5", AARCH64_INSN_REG_5, -SZ_1G);
1a7152b762288c Mark Rutland 2022-09-05 101 TEST_ADRP_CASE(test, "x6", AARCH64_INSN_REG_6, SZ_2G);
1a7152b762288c Mark Rutland 2022-09-05 102 TEST_ADRP_CASE(test, "x7", AARCH64_INSN_REG_7, -SZ_2G);
1a7152b762288c Mark Rutland 2022-09-05 103 TEST_ADRP_CASE(test, "x8", AARCH64_INSN_REG_8, SZ_2G + SZ_1G);
1a7152b762288c Mark Rutland 2022-09-05 104 TEST_ADRP_CASE(test, "x9", AARCH64_INSN_REG_9, -SZ_2G + -SZ_1G);
1a7152b762288c Mark Rutland 2022-09-05 105 TEST_ADRP_CASE(test, "x10", AARCH64_INSN_REG_10, SZ_4G - SZ_4K);
1a7152b762288c Mark Rutland 2022-09-05 106 TEST_ADRP_CASE(test, "x11", AARCH64_INSN_REG_11, -SZ_4G);
1a7152b762288c Mark Rutland 2022-09-05 107
1a7152b762288c Mark Rutland 2022-09-05 108 #undef TEST_ADRP_CASE
1a7152b762288c Mark Rutland 2022-09-05 109
1a7152b762288c Mark Rutland 2022-09-05 110 /*
1a7152b762288c Mark Rutland 2022-09-05 111 * Out-of-range immediates
1a7152b762288c Mark Rutland 2022-09-05 112 */
1a7152b762288c Mark Rutland 2022-09-05 113 KUNIT_EXPECT_EQ(test, AARCH64_BREAK_FAULT,
1a7152b762288c Mark Rutland 2022-09-05 114 aarch64_insn_gen_adr(0, SZ_4G,
1a7152b762288c Mark Rutland 2022-09-05 115 AARCH64_INSN_REG_0,
1a7152b762288c Mark Rutland 2022-09-05 116 AARCH64_INSN_ADR_TYPE_ADRP));
1a7152b762288c Mark Rutland 2022-09-05 117 KUNIT_EXPECT_EQ(test, AARCH64_BREAK_FAULT,
1a7152b762288c Mark Rutland 2022-09-05 118 aarch64_insn_gen_adr(0, -SZ_4G + -SZ_4K,
1a7152b762288c Mark Rutland 2022-09-05 119 AARCH64_INSN_REG_0,
1a7152b762288c Mark Rutland 2022-09-05 120 AARCH64_INSN_ADR_TYPE_ADRP));
1a7152b762288c Mark Rutland 2022-09-05 121 }
1a7152b762288c Mark Rutland 2022-09-05 122
f511ac384b139a Mark Rutland 2022-09-06 123 void test_insn_ldxr(struct kunit *test)
f511ac384b139a Mark Rutland 2022-09-06 124 {
f511ac384b139a Mark Rutland 2022-09-06 125 /*
f511ac384b139a Mark Rutland 2022-09-06 126 * TODO: test size, order
f511ac384b139a Mark Rutland 2022-09-06 127 */
f511ac384b139a Mark Rutland 2022-09-06 128 #define TEST_LDXR_CASE(test, asm_insn, asm_rt, gen_rt, asm_rn, gen_rn, gen_size, \
f511ac384b139a Mark Rutland 2022-09-06 129 gen_order) \
f511ac384b139a Mark Rutland 2022-09-06 130 do { \
f511ac384b139a Mark Rutland 2022-09-06 131 u32 gen_insn = aarch64_insn_gen_load_store_ex(gen_rt, gen_rn, \
f511ac384b139a Mark Rutland 2022-09-06 132 AARCH64_INSN_REG_ZR, \
f511ac384b139a Mark Rutland 2022-09-06 133 gen_size, gen_order); \
f511ac384b139a Mark Rutland 2022-09-06 134 u32 obj_insn = INSN_AS_U32(asm_insn " " asm_rt ", [" asm_rn "]"); \
f511ac384b139a Mark Rutland 2022-09-06 @135 u32 obj_rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, obj_insn); \
f511ac384b139a Mark Rutland 2022-09-06 @136 u32 obj_rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, obj_insn); \
f511ac384b139a Mark Rutland 2022-09-06 @137 u32 obj_rs = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RS, obj_insn); \
f511ac384b139a Mark Rutland 2022-09-06 @138 u32 obj_rt2 = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT2, obj_insn); \
f511ac384b139a Mark Rutland 2022-09-06 139 KUNIT_EXPECT_TRUE(test, aarch64_insn_is_ldxr(obj_insn)); \
f511ac384b139a Mark Rutland 2022-09-06 140 KUNIT_EXPECT_EQ(test, obj_rt, gen_rt); \
f511ac384b139a Mark Rutland 2022-09-06 141 KUNIT_EXPECT_EQ(test, obj_rn, gen_rn); \
f511ac384b139a Mark Rutland 2022-09-06 142 KUNIT_EXPECT_EQ(test, obj_rs, AARCH64_INSN_REG_ZR); \
f511ac384b139a Mark Rutland 2022-09-06 143 KUNIT_EXPECT_EQ(test, obj_rt2, AARCH64_INSN_REG_ZR); \
f511ac384b139a Mark Rutland 2022-09-06 144 KUNIT_EXPECT_EQ(test, obj_insn, gen_insn); \
f511ac384b139a Mark Rutland 2022-09-06 145 } while (0)
f511ac384b139a Mark Rutland 2022-09-06 146
f511ac384b139a Mark Rutland 2022-09-06 147 TEST_LDXR_CASE(test, "ldaxr",
f511ac384b139a Mark Rutland 2022-09-06 148 "x0", AARCH64_INSN_REG_0,
f511ac384b139a Mark Rutland 2022-09-06 149 "x1", AARCH64_INSN_REG_1,
f511ac384b139a Mark Rutland 2022-09-06 150 AARCH64_INSN_SIZE_64, AARCH64_INSN_LDST_LOAD_ACQ_EX);
f511ac384b139a Mark Rutland 2022-09-06 151
f511ac384b139a Mark Rutland 2022-09-06 152 TEST_LDXR_CASE(test, "ldaxr",
f511ac384b139a Mark Rutland 2022-09-06 153 "w0", AARCH64_INSN_REG_0,
f511ac384b139a Mark Rutland 2022-09-06 154 "x1", AARCH64_INSN_REG_1,
f511ac384b139a Mark Rutland 2022-09-06 155 AARCH64_INSN_SIZE_32, AARCH64_INSN_LDST_LOAD_ACQ_EX);
f511ac384b139a Mark Rutland 2022-09-06 156
f511ac384b139a Mark Rutland 2022-09-06 157 TEST_LDXR_CASE(test, "ldaxrh",
f511ac384b139a Mark Rutland 2022-09-06 158 "w0", AARCH64_INSN_REG_0,
f511ac384b139a Mark Rutland 2022-09-06 159 "x1", AARCH64_INSN_REG_1,
f511ac384b139a Mark Rutland 2022-09-06 160 AARCH64_INSN_SIZE_16, AARCH64_INSN_LDST_LOAD_ACQ_EX);
f511ac384b139a Mark Rutland 2022-09-06 161
f511ac384b139a Mark Rutland 2022-09-06 162 TEST_LDXR_CASE(test, "ldaxrb",
f511ac384b139a Mark Rutland 2022-09-06 163 "w0", AARCH64_INSN_REG_0,
f511ac384b139a Mark Rutland 2022-09-06 164 "x1", AARCH64_INSN_REG_1,
f511ac384b139a Mark Rutland 2022-09-06 165 AARCH64_INSN_SIZE_8, AARCH64_INSN_LDST_LOAD_ACQ_EX);
f511ac384b139a Mark Rutland 2022-09-06 166
f511ac384b139a Mark Rutland 2022-09-06 167 TEST_LDXR_CASE(test, "ldxr",
f511ac384b139a Mark Rutland 2022-09-06 168 "x0", AARCH64_INSN_REG_0,
f511ac384b139a Mark Rutland 2022-09-06 169 "x1", AARCH64_INSN_REG_1,
f511ac384b139a Mark Rutland 2022-09-06 170 AARCH64_INSN_SIZE_64, AARCH64_INSN_LDST_LOAD_EX);
f511ac384b139a Mark Rutland 2022-09-06 171
f511ac384b139a Mark Rutland 2022-09-06 172 TEST_LDXR_CASE(test, "ldxr",
f511ac384b139a Mark Rutland 2022-09-06 173 "w0", AARCH64_INSN_REG_0,
f511ac384b139a Mark Rutland 2022-09-06 174 "x1", AARCH64_INSN_REG_1,
f511ac384b139a Mark Rutland 2022-09-06 175 AARCH64_INSN_SIZE_32, AARCH64_INSN_LDST_LOAD_EX);
f511ac384b139a Mark Rutland 2022-09-06 176
f511ac384b139a Mark Rutland 2022-09-06 177 TEST_LDXR_CASE(test, "ldxrh",
f511ac384b139a Mark Rutland 2022-09-06 178 "w0", AARCH64_INSN_REG_0,
f511ac384b139a Mark Rutland 2022-09-06 179 "x1", AARCH64_INSN_REG_1,
f511ac384b139a Mark Rutland 2022-09-06 180 AARCH64_INSN_SIZE_16, AARCH64_INSN_LDST_LOAD_EX);
f511ac384b139a Mark Rutland 2022-09-06 181
f511ac384b139a Mark Rutland 2022-09-06 182 TEST_LDXR_CASE(test, "ldxrb",
f511ac384b139a Mark Rutland 2022-09-06 183 "w0", AARCH64_INSN_REG_0,
f511ac384b139a Mark Rutland 2022-09-06 184 "x1", AARCH64_INSN_REG_1,
f511ac384b139a Mark Rutland 2022-09-06 185 AARCH64_INSN_SIZE_8, AARCH64_INSN_LDST_LOAD_EX);
f511ac384b139a Mark Rutland 2022-09-06 186
:::::: The code at line 43 was first introduced by commit
:::::: 1a7152b762288c600b1d03d64495ce6beccc7d0c arm64: insn: add tests for ADR/ADRP manipulation
:::::: TO: Mark Rutland <mark.rutland@....com>
:::::: CC: Mark Rutland <mark.rutland@....com>
--
0-DAY CI Kernel Test Service
https://01.org/lkp
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