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Message-ID: <cover.1663025154.git.pawan.kumar.gupta@linux.intel.com>
Date: Mon, 12 Sep 2022 16:38:44 -0700
From: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
To: Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
"H. Peter Anvin" <hpa@...or.com>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Pavel Machek <pavel@....cz>,
Andrew Cooper <Andrew.Cooper3@...rix.com>, degoede@...hat.com
Cc: linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
Daniel Sneddon <daniel.sneddon@...ux.intel.com>,
antonio.gomez.iglesias@...ux.intel.com
Subject: [PATCH 0/3] Check enumeration before MSR save/restore
Hi,
This patchset is to fix the "unchecked MSR access error" [1] during S3
resume. Patch 1/3 adds a feature bit for MSR_IA32_TSX_CTRL.
Patch 2/3 adds a feature bit for MSR_AMD64_LS_CFG.
Patch 3/3 adds check for feature bit before adding any speculation
control MSR to the list of MSRs to save/restore.
[1] https://lore.kernel.org/lkml/20220906201743.436091-1-hdegoede@redhat.com/
Pawan Gupta (3):
x86/tsx: Add feature bit for TSX control MSR support
x86/cpu/amd: Add feature bit for MSR_AMD64_LS_CFG enumeration
x86/pm: Add enumeration check before spec MSRs save/restore setup
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/kernel/cpu/amd.c | 3 +++
arch/x86/kernel/cpu/tsx.c | 30 +++++++++++++++---------------
arch/x86/power/cpu.c | 23 ++++++++++++++++-------
4 files changed, 36 insertions(+), 22 deletions(-)
base-commit: 80e78fcce86de0288793a0ef0f6acf37656ee4cf
--
2.37.2
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